Lines Matching refs:AT_READ_REG
161 regs_buff[0] = AT_READ_REG(hw, REG_VPD_CAP);
162 regs_buff[1] = AT_READ_REG(hw, REG_SPI_FLASH_CTRL);
163 regs_buff[2] = AT_READ_REG(hw, REG_SPI_FLASH_CONFIG);
164 regs_buff[3] = AT_READ_REG(hw, REG_TWSI_CTRL);
165 regs_buff[4] = AT_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
166 regs_buff[5] = AT_READ_REG(hw, REG_MASTER_CTRL);
167 regs_buff[6] = AT_READ_REG(hw, REG_MANUAL_TIMER_INIT);
168 regs_buff[7] = AT_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
169 regs_buff[8] = AT_READ_REG(hw, REG_GPHY_CTRL);
170 regs_buff[9] = AT_READ_REG(hw, REG_CMBDISDMA_TIMER);
171 regs_buff[10] = AT_READ_REG(hw, REG_IDLE_STATUS);
172 regs_buff[11] = AT_READ_REG(hw, REG_MDIO_CTRL);
173 regs_buff[12] = AT_READ_REG(hw, REG_SERDES_LOCK);
174 regs_buff[13] = AT_READ_REG(hw, REG_MAC_CTRL);
175 regs_buff[14] = AT_READ_REG(hw, REG_MAC_IPG_IFG);
176 regs_buff[15] = AT_READ_REG(hw, REG_MAC_STA_ADDR);
177 regs_buff[16] = AT_READ_REG(hw, REG_MAC_STA_ADDR+4);
178 regs_buff[17] = AT_READ_REG(hw, REG_RX_HASH_TABLE);
179 regs_buff[18] = AT_READ_REG(hw, REG_RX_HASH_TABLE+4);
180 regs_buff[19] = AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
181 regs_buff[20] = AT_READ_REG(hw, REG_MTU);
182 regs_buff[21] = AT_READ_REG(hw, REG_WOL_CTRL);
183 regs_buff[22] = AT_READ_REG(hw, REG_SRAM_TRD_ADDR);
184 regs_buff[23] = AT_READ_REG(hw, REG_SRAM_TRD_LEN);
185 regs_buff[24] = AT_READ_REG(hw, REG_SRAM_RXF_ADDR);
186 regs_buff[25] = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
187 regs_buff[26] = AT_READ_REG(hw, REG_SRAM_TXF_ADDR);
188 regs_buff[27] = AT_READ_REG(hw, REG_SRAM_TXF_LEN);
189 regs_buff[28] = AT_READ_REG(hw, REG_SRAM_TCPH_ADDR);
190 regs_buff[29] = AT_READ_REG(hw, REG_SRAM_PKTH_ADDR);