Lines Matching refs:AT_WRITE_REG
106 AT_WRITE_REG(hw, REG_PCIE_PHYMISC, data);
117 AT_WRITE_REG(hw, REG_PCIE_PHYMISC2, data);
134 AT_WRITE_REG(hw, PCI_COMMAND, pci_cmd);
148 AT_WRITE_REG(hw, REG_PCIE_UC_SEVERITY, data);
152 AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, data);
158 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
160 AT_WRITE_REG(hw, REG_GPHY_CTRL,
173 AT_WRITE_REG(&adapter->hw, REG_ISR, 0x7FFFFFFF);
174 AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
186 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
187 AT_WRITE_REG(&adapter->hw, REG_ISR, ISR_DIS_INT);
401 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
404 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
437 AT_WRITE_REG(&adapter->hw, REG_MAC_CTRL, mac_ctrl_data);
524 AT_WRITE_REG(&adapter->hw, 0x1414, phy_data);
1021 AT_WRITE_REG(hw, REG_TX_BASE_ADDR_HI,
1025 AT_WRITE_REG(hw, REG_NTPD_HEAD_ADDR_LO,
1028 AT_WRITE_REG(hw, REG_HTPD_HEAD_ADDR_LO,
1031 AT_WRITE_REG(hw, REG_TPD_RING_SIZE,
1036 AT_WRITE_REG(hw, REG_RX_BASE_ADDR_HI,
1039 AT_WRITE_REG(hw, atl1c_rfd_addr_lo_regs[i],
1042 AT_WRITE_REG(hw, REG_RFD_RING_SIZE,
1044 AT_WRITE_REG(hw, REG_RX_BUF_SIZE,
1049 AT_WRITE_REG(hw, atl1c_rrd_addr_lo_regs[i],
1051 AT_WRITE_REG(hw, REG_RRD_RING_SIZE,
1055 AT_WRITE_REG(hw, REG_CMB_BASE_ADDR_LO, cmb->dma & AT_DMA_LO_ADDR_MASK);
1058 AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_HI,
1060 AT_WRITE_REG(hw, REG_SMB_BASE_ADDR_LO,
1063 AT_WRITE_REG(hw, REG_SRAM_RXF_LEN, 0x02a0L);
1064 AT_WRITE_REG(hw, REG_SRAM_TXF_LEN, 0x0100L);
1065 AT_WRITE_REG(hw, REG_SRAM_RXF_ADDR, 0x029f0000L);
1066 AT_WRITE_REG(hw, REG_SRAM_RFD0_INFO, 0x02bf02a0L);
1067 AT_WRITE_REG(hw, REG_SRAM_TXF_ADDR, 0x03bf02c0L);
1068 AT_WRITE_REG(hw, REG_SRAM_TRD_ADDR, 0x03df03c0L);
1069 AT_WRITE_REG(hw, REG_TXF_WATER_MARK, 0); /* TX watermark, to enter l1 state.*/
1070 AT_WRITE_REG(hw, REG_RXD_DMA_CTRL, 0); /* RXD threshold.*/
1077 AT_WRITE_REG(hw, REG_SERDES_LOCK, data);
1080 AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
1095 AT_WRITE_REG(hw, REG_TX_TSO_OFFLOAD_THRESH,
1115 AT_WRITE_REG(hw, REG_TXQ_CTRL, txq_ctrl_data);
1147 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
1154 AT_WRITE_REG(hw, REG_IDT_TABLE, hw->indirect_tab);
1155 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, hw->base_cpu);
1194 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
1209 AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
1213 AT_WRITE_REG(hw, REG_TWSI_CTRL, data);
1219 AT_WRITE_REG(hw, REG_MAC_CTRL, data);
1243 AT_WRITE_REG(hw, REG_RXQ_CTRL, data);
1252 AT_WRITE_REG(hw, REG_TXQ_CTRL, data);
1266 AT_WRITE_REG(hw, REG_IMR, 0);
1267 AT_WRITE_REG(hw, REG_ISR, ISR_DIS_INT);
1310 AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
1341 AT_WRITE_REG(hw, REG_LINK_CTRL, link_ctrl_data);
1403 AT_WRITE_REG(hw, REG_PM_CTRL, pm_ctrl_data);
1449 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
1466 AT_WRITE_REG(hw, REG_ISR, 0xFFFFFFFF);
1468 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
1480 AT_WRITE_REG(hw, REG_CLK_GATING_CTRL, data);
1482 AT_WRITE_REG(hw, REG_INT_RETRIG_TIMER,
1492 AT_WRITE_REG(hw, REG_IRQ_MODRT_TIMER_INIT, intr_modrt_data);
1501 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
1504 AT_WRITE_REG(hw, REG_CMB_TPD_THRESH,
1506 AT_WRITE_REG(hw, REG_CMB_TX_TIMER,
1511 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER,
1514 AT_WRITE_REG(hw, REG_MTU, hw->max_frame_size + ETH_HLEN +
1517 AT_WRITE_REG(hw, REG_HDS_CTRL, 0);
1670 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
1674 AT_WRITE_REG(hw, REG_IMR, hw->intr_mask);
1709 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
1778 AT_WRITE_REG(&adapter->hw, atl1c_rfd_prod_idx_regs[ringid],
1915 AT_WRITE_REG(&adapter->hw, REG_IMR, adapter->hw.intr_mask);
2201 AT_WRITE_REG(&adapter->hw, REG_MB_PRIO_PROD_IDX, prod_data);
2412 AT_WRITE_REG(&adapter->hw, REG_MDIO_CTRL, phy_data);
2521 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
2522 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
2523 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2528 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
2532 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_POWER_SAVING);
2536 AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl_data);
2537 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
2538 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
2559 AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);