Lines Matching refs:hw
32 int atl1c_check_eeprom_exist(struct atl1c_hw *hw)
36 AT_READ_REG(hw, REG_TWSI_DEBUG, &data);
40 AT_READ_REG(hw, REG_MASTER_CTRL, &data);
46 void atl1c_hw_set_mac_addr(struct atl1c_hw *hw)
54 value = (((u32)hw->mac_addr[2]) << 24) |
55 (((u32)hw->mac_addr[3]) << 16) |
56 (((u32)hw->mac_addr[4]) << 8) |
57 (((u32)hw->mac_addr[5])) ;
58 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
60 value = (((u32)hw->mac_addr[0]) << 8) |
61 (((u32)hw->mac_addr[1])) ;
62 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
69 static int atl1c_get_permanent_address(struct atl1c_hw *hw)
83 AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
84 if (atl1c_check_eeprom_exist(hw)) {
85 if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c_b) {
89 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
90 AT_WRITE_FLUSH(hw);
95 if (hw->nic_type == athr_l2c_b ||
96 hw->nic_type == athr_l2c_b2 ||
97 hw->nic_type == athr_l1d) {
98 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x00);
99 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
102 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
104 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
105 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
108 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
113 AT_READ_REG(hw, REG_LTSSM_ID_CTRL, <ssm_ctrl_data);
115 AT_WRITE_REG(hw, REG_LTSSM_ID_CTRL, ltssm_ctrl_data);
118 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
119 AT_READ_REG(hw, REG_WOL_CTRL, &wol_data);
122 AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
124 AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
127 AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
135 if ((hw->nic_type == athr_l1c || hw->nic_type == athr_l2c)) {
137 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
141 if (hw->nic_type == athr_l2c_b ||
142 hw->nic_type == athr_l2c_b2 ||
143 hw->nic_type == athr_l1d ||
144 hw->nic_type == athr_l1d_2) {
145 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x00);
146 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
149 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
151 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
152 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data))
155 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data);
161 AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]);
162 AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]);
167 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
175 bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value)
186 AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
188 AT_WRITE_REG(hw, REG_OTP_CTRL,
191 AT_WRITE_REG(hw, REG_EEPROM_DATA_LO, 0);
193 AT_WRITE_REG(hw, REG_EEPROM_CTRL, control);
197 AT_READ_REG(hw, REG_EEPROM_CTRL, &control);
202 AT_READ_REG(hw, REG_EEPROM_CTRL, &data);
203 AT_READ_REG(hw, REG_EEPROM_DATA_LO, p_value);
209 AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
216 * hw - Struct containing variables accessed by shared code
218 int atl1c_read_mac_addr(struct atl1c_hw *hw)
222 err = atl1c_get_permanent_address(hw);
224 random_ether_addr(hw->perm_mac_addr);
226 memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
238 u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr)
253 * hw - Struct containing variables accessed by shared code
256 void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value)
273 mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
277 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
282 * hw - Struct containing variables accessed by shared code
285 int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
294 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
298 AT_READ_REG(hw, REG_MDIO_CTRL, &val);
312 * hw - Struct containing variables accessed by shared code
316 int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data)
326 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
330 AT_READ_REG(hw, REG_MDIO_CTRL, &val);
344 * hw - Struct containing variables accessed by shared code
346 static int atl1c_phy_setup_adv(struct atl1c_hw *hw)
352 if (hw->autoneg_advertised & ADVERTISED_10baseT_Half)
354 if (hw->autoneg_advertised & ADVERTISED_10baseT_Full)
356 if (hw->autoneg_advertised & ADVERTISED_100baseT_Half)
358 if (hw->autoneg_advertised & ADVERTISED_100baseT_Full)
361 if (hw->autoneg_advertised & ADVERTISED_Autoneg)
365 if (hw->link_cap_flags & ATL1C_LINK_CAP_1000M) {
366 if (hw->autoneg_advertised & ADVERTISED_1000baseT_Half)
368 if (hw->autoneg_advertised & ADVERTISED_1000baseT_Full)
370 if (hw->autoneg_advertised & ADVERTISED_Autoneg)
375 if (atl1c_write_phy_reg(hw, MII_ADVERTISE, mii_adv_data) != 0 ||
376 atl1c_write_phy_reg(hw, MII_GIGA_CR, mii_giga_ctrl_data) != 0)
381 void atl1c_phy_disable(struct atl1c_hw *hw)
383 AT_WRITE_REGW(hw, REG_GPHY_CTRL,
387 static void atl1c_phy_magic_data(struct atl1c_hw *hw)
395 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_18);
396 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
402 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_5);
403 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
410 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_54);
411 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
418 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_4);
419 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
425 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_0);
426 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
428 if (hw->ctrl_flags & ATL1C_HIB_DISABLE) {
429 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_41);
430 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
433 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
435 atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_11);
436 if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
439 atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
443 int atl1c_phy_reset(struct atl1c_hw *hw)
445 struct atl1c_adapter *adapter = hw->adapter;
452 if (hw->ctrl_flags & ATL1C_HIB_DISABLE)
455 AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
456 AT_WRITE_FLUSH(hw);
459 AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
460 AT_WRITE_FLUSH(hw);
463 if (hw->nic_type == athr_l2c_b) {
464 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x0A);
465 atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
466 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data & 0xDFFF);
469 if (hw->nic_type == athr_l2c_b ||
470 hw->nic_type == athr_l2c_b2 ||
471 hw->nic_type == athr_l1d ||
472 hw->nic_type == athr_l1d_2) {
473 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x3B);
474 atl1c_read_phy_reg(hw, MII_DBG_DATA, &phy_data);
475 atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data & 0xFFF7);
478 if (hw->nic_type == athr_l1d) {
479 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x29);
480 atl1c_write_phy_reg(hw, MII_DBG_DATA, 0x929D);
482 if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c_b2
483 || hw->nic_type == athr_l2c || hw->nic_type == athr_l2c) {
484 atl1c_write_phy_reg(hw, MII_DBG_ADDR, 0x29);
485 atl1c_write_phy_reg(hw, MII_DBG_DATA, 0xB6DD);
487 err = atl1c_write_phy_reg(hw, MII_IER, mii_ier_data);
494 if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION))
495 atl1c_phy_magic_data(hw);
499 int atl1c_phy_init(struct atl1c_hw *hw)
501 struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
506 if ((atl1c_read_phy_reg(hw, MII_PHYSID1, &hw->phy_id1) != 0) ||
507 (atl1c_read_phy_reg(hw, MII_PHYSID2, &hw->phy_id2) != 0)) {
511 switch (hw->media_type) {
513 ret_val = atl1c_phy_setup_adv(hw);
537 hw->media_type);
542 ret_val = atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
545 hw->phy_configured = true;
553 * hw - Struct containing variables accessed by shared code
557 int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex)
563 err = atl1c_read_phy_reg(hw, MII_GIGA_PSSR, &phy_data);
593 int atl1c_phy_power_saving(struct atl1c_hw *hw)
595 struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
606 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
607 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
609 atl1c_read_phy_reg(hw, MII_LPA, &mii_lpa_data);
619 save_autoneg_advertised = hw->autoneg_advertised;
620 hw->phy_configured = false;
621 hw->autoneg_advertised = autoneg_advertised;
622 if (atl1c_restart_autoneg(hw) != 0) {
626 hw->autoneg_advertised = save_autoneg_advertised;
631 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
632 atl1c_read_phy_reg(hw, MII_BMSR, &phy_data);
634 if (atl1c_get_speed_and_duplex(hw, &speed,
652 int atl1c_restart_autoneg(struct atl1c_hw *hw)
657 err = atl1c_phy_setup_adv(hw);
662 return atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);