Lines Matching defs:lp
147 struct at91_private *lp = netdev_priv(dev);
151 if (!mii_link_ok(&lp->mii)) { /* no link */
159 read_phy(lp->phy_address, MII_BMSR, &bmsr);
160 read_phy(lp->phy_address, MII_BMCR, &bmcr);
165 read_phy(lp->phy_address, MII_LPA, &lpa);
200 struct at91_private *lp = netdev_priv(dev);
209 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
210 read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */
214 else if (lp->phy_type == MII_LXT971A_ID) {
215 read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */
219 else if (lp->phy_type == MII_BCM5221_ID) {
220 read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */
224 else if (lp->phy_type == MII_KS8721_ID) {
225 read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */
229 else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */
230 read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy);
234 else if (lp->phy_type == MII_DP83848_ID) {
235 read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */
253 struct at91_private *lp = netdev_priv(dev);
257 irq_number = lp->board_data.phy_irq_pin;
263 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
273 spin_lock_irq(&lp->lock);
276 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
277 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
279 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
281 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
282 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
284 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
286 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
288 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
290 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
292 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
294 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
295 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
297 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
299 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
300 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
302 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
303 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
305 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
309 spin_unlock_irq(&lp->lock);
317 struct at91_private *lp = netdev_priv(dev);
321 irq_number = lp->board_data.phy_irq_pin;
323 del_timer_sync(&lp->check_timer);
327 spin_lock_irq(&lp->lock);
330 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
331 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
333 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
335 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
336 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
338 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
340 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
341 read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr);
343 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
345 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
346 read_phy(lp->phy_address, MII_TPISTATUS, &dsintr);
348 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
350 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
351 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
353 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
355 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
356 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
358 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
359 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
361 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
365 spin_unlock_irq(&lp->lock);
377 struct at91_private *lp = netdev_priv(dev);
383 mod_timer(&lp->check_timer, jiffies + LINK_POLL_INTERVAL);
601 struct at91_private *lp = netdev_priv(dev);
604 spin_lock_irq(&lp->lock);
607 ret = mii_ethtool_gset(&lp->mii, cmd);
610 spin_unlock_irq(&lp->lock);
612 if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */
622 struct at91_private *lp = netdev_priv(dev);
625 spin_lock_irq(&lp->lock);
628 ret = mii_ethtool_sset(&lp->mii, cmd);
631 spin_unlock_irq(&lp->lock);
638 struct at91_private *lp = netdev_priv(dev);
641 spin_lock_irq(&lp->lock);
644 ret = mii_nway_restart(&lp->mii);
647 spin_unlock_irq(&lp->lock);
669 struct at91_private *lp = netdev_priv(dev);
675 spin_lock_irq(&lp->lock);
677 res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL);
679 spin_unlock_irq(&lp->lock);
691 struct at91_private *lp = netdev_priv(dev);
696 dlist = lp->dlist;
697 dlist_phys = lp->dlist_phys;
708 lp->rxBuffIndex = 0;
723 struct at91_private *lp = netdev_priv(dev);
729 clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */
747 spin_lock_irq(&lp->lock);
751 spin_unlock_irq(&lp->lock);
763 struct at91_private *lp = netdev_priv(dev);
780 clk_disable(lp->ether_clk); /* Disable Peripheral clock */
790 struct at91_private *lp = netdev_priv(dev);
796 lp->skb = skb;
797 lp->skb_length = skb->len;
798 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
802 at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr);
856 struct at91_private *lp = netdev_priv(dev);
862 dlist = lp->dlist;
863 while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
864 p_recv = dlist->recv_buf[lp->rxBuffIndex];
865 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */
880 if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
883 dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */
884 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */
885 lp->rxBuffIndex = 0;
887 lp->rxBuffIndex++;
897 struct at91_private *lp = netdev_priv(dev);
912 if (lp->skb) {
913 dev_kfree_skb_irq(lp->skb);
914 lp->skb = NULL;
915 dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
966 struct at91_private *lp;
984 lp = netdev_priv(dev);
985 lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
986 if (lp->dlist == NULL) {
991 lp->board_data = *board_data;
992 lp->ether_clk = ether_clk;
995 spin_lock_init(&lp->lock);
1008 if (lp->board_data.is_rmii)
1014 spin_lock_irq(&lp->lock);
1016 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
1019 lp->phy_media = PORT_FIBRE;
1027 spin_unlock_irq(&lp->lock);
1029 lp->mii.dev = dev; /* Support for ethtool */
1030 lp->mii.mdio_read = mdio_read;
1031 lp->mii.mdio_write = mdio_write;
1032 lp->mii.phy_id = phy_address;
1033 lp->mii.phy_id_mask = 0x1f;
1034 lp->mii.reg_num_mask = 0x1f;
1036 lp->phy_type = phy_type; /* Type of PHY connected */
1037 lp->phy_address = phy_address; /* MDI address of PHY */
1044 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1049 spin_lock_irq(&lp->lock);
1053 spin_unlock_irq(&lp->lock);
1057 if (!lp->board_data.phy_irq_pin) {
1058 init_timer(&lp->check_timer);
1059 lp->check_timer.data = (unsigned long)dev;
1060 lp->check_timer.function = at91ether_check_link;
1061 } else if (lp->board_data.phy_irq_pin >= 32)
1062 gpio_request(lp->board_data.phy_irq_pin, "ethernet_phy");
1070 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
1071 printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
1147 struct at91_private *lp = netdev_priv(dev);
1149 if (lp->board_data.phy_irq_pin >= 32)
1150 gpio_free(lp->board_data.phy_irq_pin);
1154 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1155 clk_put(lp->ether_clk);
1167 struct at91_private *lp = netdev_priv(net_dev);
1168 int phy_irq = lp->board_data.phy_irq_pin;
1177 clk_disable(lp->ether_clk);
1185 struct at91_private *lp = netdev_priv(net_dev);
1186 int phy_irq = lp->board_data.phy_irq_pin;
1189 clk_enable(lp->ether_clk);