Lines Matching refs:IntLatch
457 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
1710 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1716 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1902 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
2236 if ((status & IntLatch) == 0)
2304 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2310 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2311 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2352 if ((status & IntLatch) == 0)
2432 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2438 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2442 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);