Lines Matching refs:EL3_CMD
430 #define EL3_CMD 0x0e
433 /* The top five bits written to EL3_CMD are a command, the lower
462 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
657 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
942 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
1494 iowrite16(cmd, ioaddr + EL3_CMD);
1635 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1659 iowrite16(StartCoax, ioaddr + EL3_CMD);
1669 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1682 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1701 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1703 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1704 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1714 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1717 ioaddr + EL3_CMD);
1718 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1868 ioaddr + EL3_CMD);
1882 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1935 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1942 iowrite16(TxEnable, ioaddr + EL3_CMD);
1985 iowrite16(TxEnable, ioaddr + EL3_CMD);
1990 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
2005 ioaddr + EL3_CMD);
2011 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2012 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2041 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2042 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2048 iowrite16(TxEnable, ioaddr + EL3_CMD);
2073 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2084 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2104 iowrite16(TxEnable, ioaddr + EL3_CMD);
2205 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2266 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2278 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2302 ioaddr + EL3_CMD);
2303 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2304 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2310 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2374 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2383 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2430 ioaddr + EL3_CMD);
2431 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2432 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2438 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2492 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2501 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2611 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2648 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2651 iowrite16(RxDisable, ioaddr + EL3_CMD);
2652 iowrite16(TxDisable, ioaddr + EL3_CMD);
2659 iowrite16(StopCoax, ioaddr + EL3_CMD);
2661 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2769 iowrite16(DownUnstall, ioaddr + EL3_CMD);
3012 iowrite16(new_mode, ioaddr + EL3_CMD);
3180 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3181 iowrite16(RxEnable, ioaddr + EL3_CMD);
3224 vp->ioaddr + EL3_CMD);
3284 iowrite16(TotalReset, ioaddr + EL3_CMD);