Lines Matching defs:vp
576 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
654 static void window_set(struct vortex_private *vp, int window)
656 if (window != vp->window) {
657 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
658 vp->window = window;
664 window_read ## size(struct vortex_private *vp, int window, int addr) \
668 spin_lock_irqsave(&vp->window_lock, flags); \
669 window_set(vp, window); \
670 ret = ioread ## size(vp->ioaddr + addr); \
671 spin_unlock_irqrestore(&vp->window_lock, flags); \
675 window_write ## size(struct vortex_private *vp, u ## size value, \
679 spin_lock_irqsave(&vp->window_lock, flags); \
680 window_set(vp, window); \
681 iowrite ## size(value, vp->ioaddr + addr); \
682 spin_unlock_irqrestore(&vp->window_lock, flags); \
694 #define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
702 #define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
750 static void mdio_sync(struct vortex_private *vp, int bits);
752 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
833 struct vortex_private *vp = netdev_priv(dev);
836 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
927 struct vortex_private *vp;
938 vp = netdev_priv(dev);
939 ioaddr = vp->ioaddr;
1083 struct vortex_private *vp;
1110 dev = alloc_etherdev(sizeof(*vp));
1117 vp = netdev_priv(dev);
1140 vp->enable_wol = 1;
1156 vp->ioaddr = ioaddr;
1157 vp->large_frames = mtu > 1500;
1158 vp->drv_flags = vci->drv_flags;
1159 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1160 vp->io_size = vci->io_size;
1161 vp->card_idx = card_idx;
1162 vp->window = -1;
1174 vp->must_free_region = 1;
1197 spin_lock_init(&vp->lock);
1198 spin_lock_init(&vp->mii_lock);
1199 spin_lock_init(&vp->window_lock);
1200 vp->gendev = gendev;
1201 vp->mii.dev = dev;
1202 vp->mii.mdio_read = mdio_read;
1203 vp->mii.mdio_write = mdio_write;
1204 vp->mii.phy_id_mask = 0x1f;
1205 vp->mii.reg_num_mask = 0x1f;
1208 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1210 &vp->rx_ring_dma);
1212 if (!vp->rx_ring)
1215 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1216 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1225 vp->media_override = 7;
1227 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1228 if (vp->media_override != 7)
1229 vp->medialock = 1;
1230 vp->full_duplex = (option & 0x200) ? 1 : 0;
1231 vp->bus_master = (option & 16) ? 1 : 0;
1235 vp->full_duplex = 1;
1237 vp->enable_wol = 1;
1241 vp->full_duplex = 1;
1243 vp->flow_ctrl = 1;
1245 vp->enable_wol = 1;
1248 vp->mii.force_media = vp->full_duplex;
1249 vp->options = option;
1263 window_write16(vp, base + i, 0, Wn0EepromCmd);
1267 if ((window_read16(vp, 0, Wn0EepromCmd) &
1271 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1297 window_write8(vp, dev->dev_addr[i], 2, i);
1306 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1317 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1318 if (!vp->cb_fn_base) {
1327 vp->cb_fn_base);
1330 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1331 if (vp->drv_flags & INVERT_LED_PWR)
1333 if (vp->drv_flags & INVERT_MII_PWR)
1335 window_write16(vp, n, 2, Wn2_ResetOptions);
1336 if (vp->drv_flags & WNO_XCVR_PWR) {
1337 window_write16(vp, 0x0800, 0, 0);
1342 vp->info1 = eeprom[13];
1343 vp->info2 = eeprom[15];
1344 vp->capabilities = eeprom[16];
1346 if (vp->info1 & 0x8000) {
1347 vp->full_duplex = 1;
1355 vp->available_media = window_read16(vp, 3, Wn3_Options);
1356 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1357 vp->available_media = 0x40;
1358 config = window_read32(vp, 3, Wn3_Config);
1361 config, window_read16(vp, 3, Wn3_Options));
1370 vp->default_media = XCVR(config);
1371 if (vp->default_media == XCVR_NWAY)
1372 vp->has_nway = 1;
1373 vp->autoselect = AUTOSELECT(config);
1376 if (vp->media_override != 7) {
1378 print_name, vp->media_override,
1379 media_tbl[vp->media_override].name);
1380 dev->if_port = vp->media_override;
1382 dev->if_port = vp->default_media;
1384 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1388 if (vp->drv_flags & EXTRA_PREAMBLE)
1390 mdio_sync(vp, 32);
1407 vp->phys[phy_idx++] = phyx;
1419 vp->phys[0] = 24;
1421 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1422 if (vp->full_duplex) {
1424 vp->advertising &= ~0x02A0;
1425 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1428 vp->mii.phy_id = vp->phys[0];
1431 if (vp->capabilities & CapBusMaster) {
1432 vp->full_bus_master_tx = 1;
1435 (vp->info2 & 1) ? "early" : "whole-frame" );
1437 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1438 vp->bus_master = 0; /* AKPM: vortex only */
1442 if (vp->full_bus_master_tx) {
1446 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1464 vp->pm_state_valid = 1;
1465 pci_save_state(VORTEX_PCI(vp));
1476 vp->rx_ring,
1477 vp->rx_ring_dma);
1479 if (vp->must_free_region)
1490 struct vortex_private *vp = netdev_priv(dev);
1491 void __iomem *ioaddr = vp->ioaddr;
1517 struct vortex_private *vp = netdev_priv(dev);
1520 dev->name, (vp->full_duplex) ? "full" : "half");
1523 window_write16(vp,
1524 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1525 (vp->large_frames ? 0x40 : 0) |
1526 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1533 struct vortex_private *vp = netdev_priv(dev);
1539 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1540 vp->full_duplex = vp->mii.full_duplex;
1550 struct vortex_private *vp = netdev_priv(dev);
1551 void __iomem *ioaddr = vp->ioaddr;
1555 if (VORTEX_PCI(vp)) {
1556 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1557 if (vp->pm_state_valid)
1558 pci_restore_state(VORTEX_PCI(vp));
1559 err = pci_enable_device(VORTEX_PCI(vp));
1568 config = window_read32(vp, 3, Wn3_Config);
1570 if (vp->media_override != 7) {
1572 dev->name, vp->media_override,
1573 media_tbl[vp->media_override].name);
1574 dev->if_port = vp->media_override;
1575 } else if (vp->autoselect) {
1576 if (vp->has_nway) {
1584 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1591 dev->if_port = vp->default_media;
1597 init_timer(&vp->timer);
1598 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1599 vp->timer.data = (unsigned long)dev;
1600 vp->timer.function = vortex_timer; /* timer handler */
1601 add_timer(&vp->timer);
1603 init_timer(&vp->rx_oom_timer);
1604 vp->rx_oom_timer.data = (unsigned long)dev;
1605 vp->rx_oom_timer.function = rx_oom_timer;
1611 vp->full_duplex = vp->mii.force_media;
1615 window_write32(vp, config, 3, Wn3_Config);
1618 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1619 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1620 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1621 vp->mii.full_duplex = vp->full_duplex;
1639 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1644 window_write8(vp, dev->dev_addr[i], 2, i);
1646 window_write16(vp, 0, 2, i);
1648 if (vp->cb_fn_base) {
1649 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1650 if (vp->drv_flags & INVERT_LED_PWR)
1652 if (vp->drv_flags & INVERT_MII_PWR)
1654 window_write16(vp, n, 2, Wn2_ResetOptions);
1661 window_write16(vp,
1662 (window_read16(vp, 4, Wn4_Media) &
1671 window_read8(vp, 6, i);
1672 window_read16(vp, 6, 10);
1673 window_read16(vp, 6, 12);
1675 window_read8(vp, 4, 12);
1677 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1679 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1680 vp->cur_rx = vp->dirty_rx = 0;
1684 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1686 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1687 vp->cur_tx = vp->dirty_tx = 0;
1688 if (vp->drv_flags & IS_BOOMERANG)
1692 vp->rx_ring[i].status = 0;
1694 vp->tx_skbuff[i] = NULL;
1706 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1707 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1708 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1709 (vp->bus_master ? DMADone : 0);
1710 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1711 (vp->full_bus_master_rx ? 0 : RxComplete) |
1713 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1714 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1718 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1719 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1720 iowrite32(0x8000, vp->cb_fn_base + 4);
1729 struct vortex_private *vp = netdev_priv(dev);
1734 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1740 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1745 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1746 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1747 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1751 vp->rx_skbuff[i] = skb;
1756 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1762 if (vp->rx_skbuff[j]) {
1763 dev_kfree_skb(vp->rx_skbuff[j]);
1764 vp->rx_skbuff[j] = NULL;
1771 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1791 struct vortex_private *vp = netdev_priv(dev);
1792 void __iomem *ioaddr = vp->ioaddr;
1803 media_status = window_read16(vp, 4, Wn4_Media);
1836 if (vp->medialock)
1842 spin_lock_irq(&vp->lock);
1846 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1848 dev->if_port = vp->default_media;
1858 window_write16(vp,
1863 config = window_read32(vp, 3, Wn3_Config);
1865 window_write32(vp, config, 3, Wn3_Config);
1872 spin_unlock_irq(&vp->lock);
1880 mod_timer(&vp->timer, RUN_AT(next_tick));
1881 if (vp->deferred)
1887 struct vortex_private *vp = netdev_priv(dev);
1888 void __iomem *ioaddr = vp->ioaddr;
1894 window_read16(vp, 4, Wn4_NetDiag),
1895 window_read16(vp, 4, Wn4_Media),
1897 window_read16(vp, 4, Wn4_FIFODiag));
1912 if (vp->full_bus_master_tx)
1926 if (vp->full_bus_master_tx) {
1928 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1929 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1931 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1933 if (vp->drv_flags & IS_BOOMERANG)
1953 struct vortex_private *vp = netdev_priv(dev);
1954 void __iomem *ioaddr = vp->ioaddr;
1977 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1981 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
2004 (window_read16(vp, 5, 10) & ~StatsFull),
2006 vp->intr_enable &= ~StatsFull;
2011 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2012 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2016 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
2020 if (vp->full_bus_master_tx) {
2049 if (!vp->full_bus_master_tx)
2057 struct vortex_private *vp = netdev_priv(dev);
2058 void __iomem *ioaddr = vp->ioaddr;
2062 if (vp->bus_master) {
2065 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2067 spin_lock_irq(&vp->window_lock);
2068 window_set(vp, 7);
2069 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
2071 spin_unlock_irq(&vp->window_lock);
2072 vp->tx_skb = skb;
2115 struct vortex_private *vp = netdev_priv(dev);
2116 void __iomem *ioaddr = vp->ioaddr;
2118 int entry = vp->cur_tx % TX_RING_SIZE;
2119 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2125 dev->name, vp->cur_tx);
2134 if (vp->handling_irq)
2137 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2145 vp->tx_skbuff[entry] = skb;
2147 vp->tx_ring[entry].next = 0;
2150 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2152 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2155 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2157 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2161 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2163 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
2168 vp->tx_ring[entry].frag[i+1].addr =
2169 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2174 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2176 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2180 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2181 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2182 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2185 spin_lock_irqsave(&vp->lock, flags);
2188 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2190 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2191 vp->queued_packet++;
2194 vp->cur_tx++;
2195 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2206 spin_unlock_irqrestore(&vp->lock, flags);
2222 struct vortex_private *vp = netdev_priv(dev);
2228 ioaddr = vp->ioaddr;
2229 spin_lock(&vp->lock);
2241 status |= vp->deferred;
2242 vp->deferred = 0;
2252 spin_lock(&vp->window_lock);
2253 window_set(vp, 7);
2273 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2274 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2289 spin_unlock(&vp->window_lock);
2291 spin_lock(&vp->window_lock);
2292 window_set(vp, 7);
2300 vp->deferred |= status;
2301 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2303 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2306 mod_timer(&vp->timer, jiffies + 1*HZ);
2313 spin_unlock(&vp->window_lock);
2319 spin_unlock(&vp->lock);
2332 struct vortex_private *vp = netdev_priv(dev);
2337 ioaddr = vp->ioaddr;
2344 spin_lock(&vp->lock);
2345 vp->handling_irq = 1;
2362 status |= vp->deferred;
2363 vp->deferred = 0;
2381 unsigned int dirty_tx = vp->dirty_tx;
2384 while (vp->cur_tx - dirty_tx > 0) {
2387 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2390 if (vp->tx_skbuff[entry]) {
2391 struct sk_buff *skb = vp->tx_skbuff[entry];
2395 pci_unmap_single(VORTEX_PCI(vp),
2396 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2397 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2400 pci_unmap_single(VORTEX_PCI(vp),
2401 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2404 vp->tx_skbuff[entry] = NULL;
2411 vp->dirty_tx = dirty_tx;
2412 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2428 vp->deferred |= status;
2429 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2431 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2434 mod_timer(&vp->timer, jiffies + 1*HZ);
2439 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2440 iowrite32(0x8000, vp->cb_fn_base + 4);
2448 vp->handling_irq = 0;
2449 spin_unlock(&vp->lock);
2455 struct vortex_private *vp = netdev_priv(dev);
2456 void __iomem *ioaddr = vp->ioaddr;
2486 if (vp->bus_master &&
2488 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2495 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2524 struct vortex_private *vp = netdev_priv(dev);
2525 int entry = vp->cur_rx % RX_RING_SIZE;
2526 void __iomem *ioaddr = vp->ioaddr;
2528 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2533 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2550 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2560 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2563 vp->rx_skbuff[entry]->data,
2565 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2566 vp->rx_copy++;
2569 skb = vp->rx_skbuff[entry];
2570 vp->rx_skbuff[entry] = NULL;
2572 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2573 vp->rx_nocopy++;
2582 vp->rx_csumhits++;
2588 entry = (++vp->cur_rx) % RX_RING_SIZE;
2591 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2593 entry = vp->dirty_rx % RX_RING_SIZE;
2594 if (vp->rx_skbuff[entry] == NULL) {
2602 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2603 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2607 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2608 vp->rx_skbuff[entry] = skb;
2610 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2624 struct vortex_private *vp = netdev_priv(dev);
2626 spin_lock_irq(&vp->lock);
2627 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2631 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2633 spin_unlock_irq(&vp->lock);
2639 struct vortex_private *vp = netdev_priv(dev);
2640 void __iomem *ioaddr = vp->ioaddr;
2644 del_timer_sync(&vp->rx_oom_timer);
2645 del_timer_sync(&vp->timer);
2664 if (vp->full_bus_master_rx)
2666 if (vp->full_bus_master_tx)
2669 if (final_down && VORTEX_PCI(vp)) {
2670 vp->pm_state_valid = 1;
2671 pci_save_state(VORTEX_PCI(vp));
2679 struct vortex_private *vp = netdev_priv(dev);
2680 void __iomem *ioaddr = vp->ioaddr;
2691 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2695 if (vp->rx_csumhits &&
2696 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2697 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2704 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2706 if (vp->rx_skbuff[i]) {
2707 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2709 dev_kfree_skb(vp->rx_skbuff[i]);
2710 vp->rx_skbuff[i] = NULL;
2713 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2715 if (vp->tx_skbuff[i]) {
2716 struct sk_buff *skb = vp->tx_skbuff[i];
2721 pci_unmap_single(VORTEX_PCI(vp),
2722 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2723 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2726 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2729 vp->tx_skbuff[i] = NULL;
2741 struct vortex_private *vp = netdev_priv(dev);
2742 void __iomem *ioaddr = vp->ioaddr;
2744 if (vp->full_bus_master_tx) {
2749 vp->full_bus_master_tx,
2750 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2751 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2754 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2760 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2762 length = le32_to_cpu(vp->tx_ring[i].length);
2765 i, &vp->tx_ring[i], length,
2766 le32_to_cpu(vp->tx_ring[i].status));
2776 struct vortex_private *vp = netdev_priv(dev);
2777 void __iomem *ioaddr = vp->ioaddr;
2781 spin_lock_irqsave (&vp->lock, flags);
2783 spin_unlock_irqrestore (&vp->lock, flags);
2797 struct vortex_private *vp = netdev_priv(dev);
2801 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2802 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2803 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2804 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2805 dev->stats.tx_packets += window_read8(vp, 6, 6);
2806 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2808 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
2812 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2813 dev->stats.tx_bytes += window_read16(vp, 6, 12);
2815 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2816 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2817 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2818 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
2820 dev->stats.collisions = vp->xstats.tx_multiple_collisions
2821 + vp->xstats.tx_single_collisions
2822 + vp->xstats.tx_max_collisions;
2825 u8 up = window_read8(vp, 4, 13);
2833 struct vortex_private *vp = netdev_priv(dev);
2835 return mii_nway_restart(&vp->mii);
2840 struct vortex_private *vp = netdev_priv(dev);
2842 return mii_ethtool_gset(&vp->mii, cmd);
2847 struct vortex_private *vp = netdev_priv(dev);
2849 return mii_ethtool_sset(&vp->mii, cmd);
2875 struct vortex_private *vp = netdev_priv(dev);
2876 void __iomem *ioaddr = vp->ioaddr;
2879 spin_lock_irqsave(&vp->lock, flags);
2881 spin_unlock_irqrestore(&vp->lock, flags);
2883 data[0] = vp->xstats.tx_deferred;
2884 data[1] = vp->xstats.tx_max_collisions;
2885 data[2] = vp->xstats.tx_multiple_collisions;
2886 data[3] = vp->xstats.tx_single_collisions;
2887 data[4] = vp->xstats.rx_bad_ssd;
2906 struct vortex_private *vp = netdev_priv(dev);
2909 if (VORTEX_PCI(vp)) {
2910 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2912 if (VORTEX_EISA(vp))
2913 strcpy(info->bus_info, dev_name(vp->gendev));
2922 struct vortex_private *vp = netdev_priv(dev);
2924 if (!VORTEX_PCI(vp))
2930 if (vp->enable_wol)
2936 struct vortex_private *vp = netdev_priv(dev);
2938 if (!VORTEX_PCI(vp))
2945 vp->enable_wol = 1;
2947 vp->enable_wol = 0;
2975 struct vortex_private *vp = netdev_priv(dev);
2978 if(VORTEX_PCI(vp))
2979 state = VORTEX_PCI(vp)->current_state;
2984 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2985 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2987 pci_set_power_state(VORTEX_PCI(vp), state);
2999 struct vortex_private *vp = netdev_priv(dev);
3000 void __iomem *ioaddr = vp->ioaddr;
3025 struct vortex_private *vp = netdev_priv(dev);
3028 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3036 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
3040 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
3044 vp->large_frames = dev->mtu > 1500 || enable;
3046 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
3047 if (vp->large_frames)
3051 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
3071 static void mdio_delay(struct vortex_private *vp)
3073 window_read32(vp, 4, Wn4_PhysicalMgmt);
3085 static void mdio_sync(struct vortex_private *vp, int bits)
3089 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3090 mdio_delay(vp);
3091 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3093 mdio_delay(vp);
3100 struct vortex_private *vp = netdev_priv(dev);
3104 spin_lock_bh(&vp->mii_lock);
3107 mdio_sync(vp, 32);
3112 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3113 mdio_delay(vp);
3114 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3116 mdio_delay(vp);
3120 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3121 mdio_delay(vp);
3123 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3125 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3127 mdio_delay(vp);
3130 spin_unlock_bh(&vp->mii_lock);
3137 struct vortex_private *vp = netdev_priv(dev);
3141 spin_lock_bh(&vp->mii_lock);
3144 mdio_sync(vp, 32);
3149 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3150 mdio_delay(vp);
3151 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3153 mdio_delay(vp);
3157 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3158 mdio_delay(vp);
3159 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3161 mdio_delay(vp);
3164 spin_unlock_bh(&vp->mii_lock);
3171 struct vortex_private *vp = netdev_priv(dev);
3172 void __iomem *ioaddr = vp->ioaddr;
3174 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3176 if (vp->enable_wol) {
3178 window_write16(vp, 2, 7, 0x0c);
3183 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3184 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3186 vp->enable_wol = 0;
3190 if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
3194 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3202 struct vortex_private *vp;
3209 vp = netdev_priv(dev);
3211 if (vp->cb_fn_base)
3212 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3216 if (VORTEX_PCI(vp)) {
3217 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3218 if (vp->pm_state_valid)
3219 pci_restore_state(VORTEX_PCI(vp));
3220 pci_disable_device(VORTEX_PCI(vp));
3223 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3224 vp->ioaddr + EL3_CMD);
3226 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
3231 vp->rx_ring,
3232 vp->rx_ring_dma);
3233 if (vp->must_free_region)
3234 release_region(dev->base_addr, vp->io_size);
3270 struct vortex_private *vp;
3279 vp = netdev_priv(compaq_net_device);