Lines Matching defs:cc
247 brcmnand_cmd(osl_t *osh, chipcregs_t *cc, uint opcode)
249 W_REG(osh, &cc->nand_cmd_start, opcode);
251 R_REG(osh, &cc->nand_cmd_start);
257 chipcregs_t *cc = brcmnand_info.cc;
265 addr = R_REG(osh, &cc->nand_ecc_corr_addr);
267 ext_addr = R_REG(osh, &cc->nand_ecc_corr_addr_x);
269 W_REG(osh, &cc->nand_ecc_corr_addr, 0);
270 W_REG(osh, &cc->nand_ecc_corr_addr_x, 0);
278 addr = R_REG(osh, &cc->nand_ecc_unc_addr);
280 ext_addr = R_REG(osh, &cc->nand_ecc_unc_addr_x);
282 W_REG(osh, &cc->nand_ecc_unc_addr, 0);
283 W_REG(osh, &cc->nand_ecc_unc_addr_x, 0);
296 chipcregs_t *cc = brcmnand_info.cc;
301 status = R_REG(osh, &cc->nand_intfc_status);
468 chipcregs_t *cc = brcmnand_info.cc;
474 p32[i] = R_REG(osh, (uint32_t *)((uint32_t)&cc->nand_spare_rd0 + (i * 4)));
522 chipcregs_t *cc = brcmnand_info.cc;
532 W_REG(osh, &cc->nand_cmd_addr, offset);
534 brcmnand_cmd(osh, cc, NCMD_PAGE_RD);
544 *to = R_REG(osh, &cc->nand_cache_data);
551 *to = R_REG(osh, (uint32_t *)((uint32_t)&cc->nand_spare_rd0 + i));
793 chipcregs_t *cc = brcmnand_info.cc;
803 W_REG(osh, &cc->nand_cmd_addr, offset);
805 brcmnand_cmd(osh, cc, NCMD_SPARE_RD);
813 *to = R_REG(osh, (uint32_t *)((uint32_t)&cc->nand_spare_rd0 + i));
1021 chipcregs_t *cc = brcmnand_info.cc;
1034 W_REG(osh, &cc->nand_cache_data, *from);
1054 chipcregs_t *cc = brcmnand_info.cc;
1069 reg = R_REG(osh, &cc->nand_acc_control);
1071 W_REG(osh, &cc->nand_acc_control, reg);
1074 W_REG(osh, &cc->nand_cache_addr, 0);
1075 W_REG(osh, &cc->nand_cmd_addr, data_written);
1085 W_REG(osh, &cc->nand_cmd_addr, offset + mtd->writesize - NFL_SECTOR_SIZE);
1086 brcmnand_cmd(osh, cc, NCMD_PAGE_PROG);
1094 reg = R_REG(osh, &cc->nand_acc_control);
1096 W_REG(osh, &cc->nand_acc_control, reg);
1140 chipcregs_t *cc = brcmnand_info.cc;
1154 reg = R_REG(osh, &cc->nand_acc_control);
1156 W_REG(osh, &cc->nand_acc_control, reg);
1158 W_REG(osh, &cc->nand_cmd_addr, offset);
1166 W_REG(osh, (uint32_t *)((uint32_t)&cc->nand_spare_wr0 + i), *from);
1169 brcmnand_cmd(osh, cc, NCMD_SPARE_PROG);
1505 chipcregs_t *cc = brcmnand_info.cc;
1546 W_REG(osh, &cc->nand_ecc_corr_addr, 0);
1547 W_REG(osh, &cc->nand_ecc_corr_addr_x, 0);
1548 W_REG(osh, &cc->nand_ecc_unc_addr, 0);
1549 W_REG(osh, &cc->nand_ecc_unc_addr_x, 0);
1576 W_REG(osh, &cc->nand_cmd_addr, (page << chip->page_shift));
1577 brcmnand_cmd(osh, cc, NCMD_BLOCK_ERASE);
1774 chipcregs_t *cc = brcmnand_info.cc;
1780 while (R_REG(osh, &cc->nflashctrl) & NFC_START) {
1802 chipcregs_t *cc = brcmnand_info.cc;
1817 W_REG(osh, &cc->nflashcoladdr, cmd);
1821 W_REG(osh, &cc->nflashrowaddr, cmd);
1834 W_REG(osh, &cc->nflashctrl, val);
2084 chipcregs_t *cc = brcmnand_info.cc;
2092 W_REG(osh, &cc->nflashctrl, val);
2109 chipcregs_t *cc = brcmnand_info.cc;
2115 W_REG(osh, &cc->nflashdata, (unsigned int)ch);
2118 W_REG(osh, &cc->nflashctrl, val);
2198 chipcregs_t *cc = brcmnand_info.cc;
2204 status = (R_REG(osh, &cc->nflashctrl) & NFC_RDYBUSY) ? 1 : 0;
2231 chipcregs_t *cc = brcmnand_info.cc;
2255 chip->IO_ADDR_W = (void __iomem *)&cc->nflashdata;
2306 if (!(brcmnand_info.cc = ioremap_nocache(
2567 if (brcmnand_info.cc)
2568 iounmap((void *) brcmnand_info.cc);
2584 iounmap((void *) brcmnand_info.cc);