Lines Matching defs:cch
557 struct gru_context_configuration_handle *cch;
562 cch = get_cch(gru->gs_gru_base_vaddr, ctxnum);
566 lock_cch_handle(cch);
567 if (cch_interrupt_sync(cch))
579 if (cch_deallocate(cch))
581 unlock_cch_handle(cch);
593 struct gru_context_configuration_handle *cch;
596 cch = get_cch(gru->gs_gru_base_vaddr, ctxnum);
597 lock_cch_handle(cch);
598 cch->tfm_fault_bit_enable =
601 cch->tlb_int_enable = (gts->ts_user_options == GRU_OPT_MISS_FMM_INTR);
602 if (cch->tlb_int_enable) {
604 cch->tlb_int_select = gts->ts_tlb_int_select;
607 cch->req_slice_set_enable = 1;
608 cch->req_slice = gts->ts_cch_req_slice;
610 cch->req_slice_set_enable =0;
612 cch->tfm_done_bit_enable = 0;
613 cch->dsr_allocation_map = gts->ts_dsr_map;
614 cch->cbr_allocation_map = gts->ts_cbr_map;
617 cch->unmap_enable = 1;
618 cch->tfm_done_bit_enable = 1;
619 cch->cb_int_enable = 1;
620 cch->tlb_int_select = 0; /* For now, ints go to cpu 0 */
622 cch->unmap_enable = 0;
623 cch->tfm_done_bit_enable = 0;
624 cch->cb_int_enable = 0;
627 cch->asid[i] = asid + i;
628 cch->sizeavail[i] = gts->ts_sizeavail;
632 err = cch_allocate(cch);
635 "err %d: cch %p, gts %p, cbr 0x%lx, dsr 0x%lx\n",
636 err, cch, gts, gts->ts_cbr_map, gts->ts_dsr_map);
643 if (cch_start(cch))
645 unlock_cch_handle(cch);
659 struct gru_context_configuration_handle *cch;
663 cch = get_cch(gru->gs_gru_base_vaddr, ctxnum);
665 lock_cch_handle(cch);
666 if (cch->state == CCHSTATE_ACTIVE) {
669 if (cch_interrupt(cch))
672 cch->sizeavail[i] = gts->ts_sizeavail;
674 cch->tlb_int_select = gru_cpu_fault_map_id();
675 cch->tfm_fault_bit_enable =
678 if (cch_start(cch))
683 unlock_cch_handle(cch);