Lines Matching defs:ucb
41 * @ucb: UCB1x00 structure describing chip
55 void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out)
59 spin_lock_irqsave(&ucb->io_lock, flags);
60 ucb->io_dir |= out;
61 ucb->io_dir &= ~in;
63 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
64 spin_unlock_irqrestore(&ucb->io_lock, flags);
69 * @ucb: UCB1x00 structure describing chip
83 void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear)
87 spin_lock_irqsave(&ucb->io_lock, flags);
88 ucb->io_out |= set;
89 ucb->io_out &= ~clear;
91 ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
92 spin_unlock_irqrestore(&ucb->io_lock, flags);
97 * @ucb: UCB1x00 structure describing chip
107 unsigned int ucb1x00_io_read(struct ucb1x00 *ucb)
109 return ucb1x00_reg_read(ucb, UCB_IO_DATA);
114 struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
117 spin_lock_irqsave(&ucb->io_lock, flags);
119 ucb->io_out |= 1 << offset;
121 ucb->io_out &= ~(1 << offset);
123 ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
124 spin_unlock_irqrestore(&ucb->io_lock, flags);
129 struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
130 return ucb1x00_reg_read(ucb, UCB_IO_DATA) & (1 << offset);
135 struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
138 spin_lock_irqsave(&ucb->io_lock, flags);
139 ucb->io_dir &= ~(1 << offset);
140 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
141 spin_unlock_irqrestore(&ucb->io_lock, flags);
149 struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
152 spin_lock_irqsave(&ucb->io_lock, flags);
153 ucb->io_dir |= (1 << offset);
154 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
157 ucb->io_out |= 1 << offset;
159 ucb->io_out &= ~(1 << offset);
160 ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
161 spin_unlock_irqrestore(&ucb->io_lock, flags);
177 * @ucb: UCB1x00 structure describing chip
191 void ucb1x00_adc_enable(struct ucb1x00 *ucb)
193 down(&ucb->adc_sem);
195 ucb->adc_cr |= UCB_ADC_ENA;
197 ucb1x00_enable(ucb);
198 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
203 * @ucb: UCB1x00 structure describing chip
217 unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync)
224 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel);
225 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START);
228 val = ucb1x00_reg_read(ucb, UCB_ADC_DATA);
241 * @ucb: UCB1x00 structure describing chip
245 void ucb1x00_adc_disable(struct ucb1x00 *ucb)
247 ucb->adc_cr &= ~UCB_ADC_ENA;
248 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
249 ucb1x00_disable(ucb);
251 up(&ucb->adc_sem);
264 struct ucb1x00 *ucb = devid;
268 ucb1x00_enable(ucb);
269 isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS);
270 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr);
271 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
273 for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++)
276 ucb1x00_disable(ucb);
283 * @ucb: UCB1x00 structure describing chip
298 int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid)
304 irq = ucb->irq_handler + idx;
307 spin_lock_irq(&ucb->lock);
313 spin_unlock_irq(&ucb->lock);
320 * @ucb: UCB1x00 structure describing chip
328 void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges)
333 spin_lock_irqsave(&ucb->lock, flags);
335 ucb1x00_enable(ucb);
337 ucb->irq_ris_enbl |= 1 << idx;
338 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
341 ucb->irq_fal_enbl |= 1 << idx;
342 ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
344 ucb1x00_disable(ucb);
345 spin_unlock_irqrestore(&ucb->lock, flags);
351 * @ucb: UCB1x00 structure describing chip
357 void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges)
362 spin_lock_irqsave(&ucb->lock, flags);
364 ucb1x00_enable(ucb);
366 ucb->irq_ris_enbl &= ~(1 << idx);
367 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
370 ucb->irq_fal_enbl &= ~(1 << idx);
371 ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
373 ucb1x00_disable(ucb);
374 spin_unlock_irqrestore(&ucb->lock, flags);
380 * @ucb: UCB1x00 structure describing chip
391 int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid)
399 irq = ucb->irq_handler + idx;
402 spin_lock_irq(&ucb->lock);
404 ucb->irq_ris_enbl &= ~(1 << idx);
405 ucb->irq_fal_enbl &= ~(1 << idx);
407 ucb1x00_enable(ucb);
408 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
409 ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
410 ucb1x00_disable(ucb);
416 spin_unlock_irq(&ucb->lock);
424 static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv)
431 dev->ucb = ucb;
437 list_add(&dev->dev_node, &ucb->devs);
473 static int ucb1x00_detect_irq(struct ucb1x00 *ucb)
486 ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
487 ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
488 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
489 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
494 ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
495 ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
500 while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0);
501 ucb1x00_reg_write(ucb, UCB_ADC_CR, 0);
506 ucb1x00_reg_write(ucb, UCB_IE_RIS, 0);
507 ucb1x00_reg_write(ucb, UCB_IE_FAL, 0);
508 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
509 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
519 struct ucb1x00 *ucb = classdev_to_ucb1x00(dev);
520 kfree(ucb);
530 struct ucb1x00 *ucb;
544 ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL);
546 if (!ucb)
550 ucb->dev.class = &ucb1x00_class;
551 ucb->dev.parent = &mcp->attached_device;
552 dev_set_name(&ucb->dev, "ucb1x00");
554 spin_lock_init(&ucb->lock);
555 spin_lock_init(&ucb->io_lock);
556 sema_init(&ucb->adc_sem, 1);
558 ucb->id = id;
559 ucb->mcp = mcp;
560 ucb->irq = ucb1x00_detect_irq(ucb);
561 if (ucb->irq == NO_IRQ) {
567 ucb->gpio.base = -1;
569 ucb->gpio.label = dev_name(&ucb->dev);
570 ucb->gpio.base = mcp->gpio_base;
571 ucb->gpio.ngpio = 10;
572 ucb->gpio.set = ucb1x00_gpio_set;
573 ucb->gpio.get = ucb1x00_gpio_get;
574 ucb->gpio.direction_input = ucb1x00_gpio_direction_input;
575 ucb->gpio.direction_output = ucb1x00_gpio_direction_output;
576 ret = gpiochip_add(&ucb->gpio);
580 dev_info(&ucb->dev, "gpio_base not set so no gpiolib support");
582 ret = request_irq(ucb->irq, ucb1x00_irq, IRQF_TRIGGER_RISING,
583 "UCB1x00", ucb);
586 ucb->irq, ret);
590 mcp_set_drvdata(mcp, ucb);
592 ret = device_register(&ucb->dev);
597 INIT_LIST_HEAD(&ucb->devs);
599 list_add(&ucb->node, &ucb1x00_devices);
601 ucb1x00_add_dev(ucb, drv);
608 free_irq(ucb->irq, ucb);
610 if (ucb->gpio.base != -1)
611 temp = gpiochip_remove(&ucb->gpio);
613 kfree(ucb);
622 struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
627 list_del(&ucb->node);
628 list_for_each_safe(l, n, &ucb->devs) {
634 if (ucb->gpio.base != -1) {
635 ret = gpiochip_remove(&ucb->gpio);
637 dev_err(&ucb->dev, "Can't remove gpio chip: %d\n", ret);
640 free_irq(ucb->irq, ucb);
641 device_unregister(&ucb->dev);
646 struct ucb1x00 *ucb;
651 list_for_each_entry(ucb, &ucb1x00_devices, node) {
652 ucb1x00_add_dev(ucb, drv);
673 struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
677 list_for_each_entry(dev, &ucb->devs, dev_node) {
687 struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
690 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
692 list_for_each_entry(dev, &ucb->devs, dev_node) {