Lines Matching refs:status
41 * The Primary Interrupt Handler (PIH) stage exposes status bits saying
47 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
298 /* Wait for IRQ, then read PIH irq status (also blocking) */
316 /* these handlers deal with the relevant SIH irq status */
333 if (d->status & IRQ_DISABLED)
380 int status;
401 status = twl_i2c_write(sih->module, buf,
403 if (status < 0)
405 status, sih->name, "IMR");
415 status = twl_i2c_write_u8(sih->module,
418 if (status < 0)
420 status, sih->name, "SIH_CTRL");
437 /* Clear pending interrupt status. Either the read was
443 status = twl_i2c_read(sih->module, rxbuf,
445 if (status < 0)
447 status, sih->name, "ISR");
450 status = twl_i2c_write(sih->module, buf,
501 int status;
519 status = twl_i2c_write(sih->module, imr.bytes,
521 if (status)
523 "write", status);
532 int status;
550 status = twl_i2c_read(sih->module, bytes + 1,
552 if (status) {
554 "read", status);
574 if (d->status & IRQ_TYPE_EDGE_RISING)
576 if (d->status & IRQ_TYPE_EDGE_FALLING)
584 status = twl_i2c_write(sih->module, bytes,
586 if (status)
588 "write", status);
639 if ((desc->status & IRQ_TYPE_SENSE_MASK) != trigger) {
640 desc->status &= ~IRQ_TYPE_SENSE_MASK;
641 desc->status |= trigger;
660 int status;
668 status = twl_i2c_read(sih->module, isr.bytes,
671 return (status < 0) ? status : le32_to_cpu(isr.word);
720 int status = -EINVAL;
732 status = 0;
736 if (status < 0)
737 return status;
743 status = 0;
760 status = irq_base;
771 return status;
784 int status;
792 status = twl4030_init_sih_modules(twl_irq_line);
793 if (status < 0)
794 return status;
822 status = twl4030_sih_setup(TWL4030_MODULE_INT);
823 if (status < 0) {
824 pr_err("twl4030: sih_setup PWR INT --> %d\n", status);
833 status = request_irq(irq_num, handle_twl4030_pih, IRQF_DISABLED,
835 if (status < 0) {
836 pr_err("twl4030: could not claim irq%d: %d\n", irq_num, status);
844 status = PTR_ERR(task);
847 return status;
857 return status;