Lines Matching refs:U32
352 U32 Word32;
511 U32 MsgContext; /* 08h */
514 U32 PageAddress; /* 18h */
542 U32 MsgContext; /* 08h */
545 U32 IOCLogInfo; /* 10h */
635 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
654 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
664 U32 Reserved1; /* 04h */
673 U32 ISVolumeSettings; /* 48h */
674 U32 IMEVolumeSettings; /* 4Ch */
675 U32 IMVolumeSettings; /* 50h */
676 U32 Reserved3; /* 54h */
677 U32 Reserved4; /* 58h */
678 U32 Reserved5; /* 5Ch */
685 U32 Reserved8; /* 68h */
686 U32 Reserved9; /* 6Ch */
728 U32 Reserved3; /* 10h */
729 U32 Reserved4; /* 14h */
743 U32 ProductSpecificInfo;/* 04h */
752 U32 Pinout; /* 00h */
757 U32 Reserved2; /* 18h */
793 U32 Reserved1; /* 04h */
794 U32 Reserved2; /* 08h */
795 U32 Flags; /* 0Ch */
813 U32 ProductSpecificInfo;/* 04h */
823 U32 ProductSpecificInfo;/* 04h */
833 U32 ProductSpecificInfo;/* 04h */
857 U32 Flags; /* 04h */
889 U32 Flags; /* 04h */
890 U32 BiosVersion; /* 08h */
892 U32 Reserved1; /* 1Ch */
938 U32 Reserved1; /* 04h */
953 U32 TotalNVStore; /* 04h */
954 U32 FreeNVStore; /* 08h */
959 U32 ClassCode; /* 14h */
971 U32 Flags; /* 04h */
972 U32 CoalescingTimeout; /* 08h */
1030 U32 CapabilitiesFlags; /* 04h */
1138 U32 Reserved1; /* 04h */
1151 U32 CapabilitiesFlags; /* 04h */
1163 U32 Reserved5; /* 14h */
1164 U32 SupportedStripeSizeMapIS; /* 18h */
1165 U32 SupportedStripeSizeMapIME; /* 1Ch */
1166 U32 Reserved6; /* 20h */
1174 U32 IRNvsramVersion; /* 30h */
1175 U32 Reserved11; /* 34h */
1176 U32 Reserved12; /* 38h */
1202 U32 BiosOptions; /* 04h */
1203 U32 IOCSettings; /* 08h */
1204 U32 Reserved1; /* 0Ch */
1205 U32 DeviceSettings; /* 10h */
1271 U32 Reserved1; /* 00h */
1272 U32 Reserved2; /* 04h */
1273 U32 Reserved3; /* 08h */
1274 U32 Reserved4; /* 0Ch */
1275 U32 Reserved5; /* 10h */
1276 U32 Reserved6; /* 14h */
1277 U32 Reserved7; /* 18h */
1278 U32 Reserved8; /* 1Ch */
1279 U32 Reserved9; /* 20h */
1280 U32 Reserved10; /* 24h */
1281 U32 Reserved11; /* 28h */
1282 U32 Reserved12; /* 2Ch */
1283 U32 Reserved13; /* 30h */
1284 U32 Reserved14; /* 34h */
1285 U32 Reserved15; /* 38h */
1286 U32 Reserved16; /* 3Ch */
1287 U32 Reserved17; /* 40h */
1296 U32 Reserved2; /* 04h */
1297 U32 Reserved3; /* 08h */
1298 U32 Reserved4; /* 0Ch */
1300 U32 Reserved5; /* 18h */
1301 U32 Reserved6; /* 1Ch */
1302 U32 Reserved7; /* 20h */
1303 U32 Reserved8; /* 24h */
1304 U32 Reserved9; /* 28h */
1305 U32 Reserved10; /* 2Ch */
1306 U32 Reserved11; /* 30h */
1307 U32 Reserved12; /* 34h */
1308 U32 Reserved13; /* 38h */
1309 U32 Reserved14; /* 3Ch */
1310 U32 Reserved15; /* 40h */
1318 U32 Reserved1; /* 04h */
1319 U32 Reserved2; /* 08h */
1320 U32 Reserved3; /* 0Ch */
1322 U32 Reserved4; /* 18h */
1323 U32 Reserved5; /* 1Ch */
1324 U32 Reserved6; /* 20h */
1325 U32 Reserved7; /* 24h */
1326 U32 Reserved8; /* 28h */
1327 U32 Reserved9; /* 2Ch */
1328 U32 Reserved10; /* 30h */
1329 U32 Reserved11; /* 34h */
1330 U32 Reserved12; /* 38h */
1331 U32 Reserved13; /* 3Ch */
1332 U32 Reserved14; /* 40h */
1341 U32 Reserved2; /* 04h */
1342 U32 Reserved3; /* 08h */
1343 U32 Reserved4; /* 0Ch */
1345 U32 Reserved5; /* 18h */
1346 U32 Reserved6; /* 1Ch */
1347 U32 Reserved7; /* 20h */
1348 U32 Reserved8; /* 24h */
1349 U32 Reserved9; /* 28h */
1350 U32 Reserved10; /* 2Ch */
1351 U32 Reserved11; /* 30h */
1352 U32 Reserved12; /* 34h */
1353 U32 Reserved13; /* 38h */
1354 U32 Reserved14; /* 3Ch */
1355 U32 Reserved15; /* 40h */
1361 U32 Reserved1; /* 08h */
1362 U32 Reserved2; /* 0Ch */
1364 U32 Reserved3; /* 18h */
1365 U32 Reserved4; /* 1Ch */
1366 U32 Reserved5; /* 20h */
1367 U32 Reserved6; /* 24h */
1368 U32 Reserved7; /* 28h */
1369 U32 Reserved8; /* 2Ch */
1370 U32 Reserved9; /* 30h */
1371 U32 Reserved10; /* 34h */
1372 U32 Reserved11; /* 38h */
1373 U32 Reserved12; /* 3Ch */
1374 U32 Reserved13; /* 40h */
1380 U32 Reserved1; /* 08h */
1381 U32 Reserved2; /* 0Ch */
1383 U32 Reserved3; /* 18h */
1384 U32 Reserved4; /* 1Ch */
1385 U32 Reserved5; /* 20h */
1386 U32 Reserved6; /* 24h */
1387 U32 Reserved7; /* 28h */
1388 U32 Reserved8; /* 2Ch */
1389 U32 Reserved9; /* 30h */
1390 U32 Reserved10; /* 34h */
1391 U32 Reserved11; /* 38h */
1392 U32 Reserved12; /* 3Ch */
1393 U32 Reserved13; /* 40h */
1399 U32 Reserved1; /* 08h */
1400 U32 Reserved2; /* 0Ch */
1404 U32 Reserved4; /* 1Ch */
1405 U32 Reserved5; /* 20h */
1406 U32 Reserved6; /* 24h */
1407 U32 Reserved7; /* 28h */
1408 U32 Reserved8; /* 2Ch */
1409 U32 Reserved9; /* 30h */
1410 U32 Reserved10; /* 34h */
1411 U32 Reserved11; /* 38h */
1412 U32 Reserved12; /* 3Ch */
1413 U32 Reserved13; /* 40h */
1431 U32 Reserved1; /* 04h */
1432 U32 Reserved2; /* 08h */
1433 U32 Reserved3; /* 0Ch */
1434 U32 Reserved4; /* 10h */
1435 U32 Reserved5; /* 14h */
1436 U32 Reserved6; /* 18h */
1472 U32 Capabilities; /* 04h */
1473 U32 PhysicalInterface; /* 08h */
1521 U32 Configuration; /* 04h */
1522 U32 OnBusTimerValue; /* 08h */
1552 U32 PortFlags; /* 04h */
1553 U32 PortSettings; /* 08h */
1605 U32 NegotiatedParameters; /* 04h */
1606 U32 Information; /* 08h */
1637 U32 RequestedParameters; /* 04h */
1638 U32 Reserved; /* 08h */
1639 U32 Configuration; /* 0Ch */
1670 U32 DomainValidation; /* 04h */
1671 U32 ParityPipeSelect; /* 08h */
1672 U32 DataPipeSelect; /* 0Ch */
1731 U32 Flags; /* 04h */
1736 U32 PortIdentifier; /* 0Ch */
1739 U32 SupportedServiceClass; /* 20h */
1740 U32 SupportedSpeeds; /* 24h */
1741 U32 CurrentSpeed; /* 28h */
1742 U32 MaxFrameSize; /* 2Ch */
1745 U32 DiscoveredPortsCount; /* 40h */
1746 U32 MaxInitiators; /* 44h */
1820 U32 Flags; /* 04h */
1853 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1854 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1855 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1856 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1904 U32 Did;
1945 U32 PortFlags; /* 04h */
1946 U32 PortSettings; /* 08h */
1992 U32 Reserved; /* 04h */
2018 U32 Reserved; /* 04h */
2029 U32 BitVector[8]; /* 04h */
2039 U32 Reserved; /* 04h */
2042 U32 UnitType; /* 18h */
2043 U32 PhysicalPortNumber; /* 1Ch */
2044 U32 NumAttachedNodes; /* 20h */
2156 U32 HwConfig1; /* 08h */
2157 U32 HwConfig2; /* 0Ch */
2193 U32 PortIdentifier; /* 14h */
2313 U32 MaxLBA; /* 10h */
2314 U32 MaxLBAHigh; /* 14h */
2315 U32 StripeSize; /* 18h */
2316 U32 Reserved2; /* 1Ch */
2317 U32 Reserved3; /* 20h */
2348 U32 Reserved1; /* 48h */
2349 U32 Reserved2; /* 4Ch */
2425 U32 Reserved1; /* 0Ch */
2430 U32 MaxLBA; /* 68h */
2470 U32 Reserved1; /* 08h */
2487 U32 PacketPrePad; /* 08h */
2503 U32 MinPacketSize; /* 08h */
2504 U32 MaxPacketSize; /* 0Ch */
2505 U32 HardwareAddressLow; /* 10h */
2506 U32 HardwareAddressHigh; /* 14h */
2507 U32 MaxWireSpeedLow; /* 18h */
2508 U32 MaxWireSpeedHigh; /* 1Ch */
2509 U32 BucketsRemaining; /* 20h */
2510 U32 MaxReplySize; /* 24h */
2511 U32 NegWireSpeedLow; /* 28h */
2512 U32 NegWireSpeedHigh; /* 2Ch */
2549 U32 ControllerPhyDeviceInfo;/* 04h */
2552 U32 DiscoveryStatus; /* 0Ch */
2622 U32 ControllerPhyDeviceInfo; /* 04h */
2750 U32 Reserved1; /* 08h */
2751 U32 MaxInvalidDwordCount; /* 0Ch */
2752 U32 InvalidDwordCountTime; /* 10h */
2753 U32 MaxRunningDisparityErrorCount; /* 14h */
2754 U32 RunningDisparityErrorTime; /* 18h */
2755 U32 MaxLossDwordSynchCount; /* 1Ch */
2756 U32 LossDwordSynchCountTime; /* 20h */
2757 U32 MaxPhyResetProblemCount; /* 24h */
2758 U32 PhyResetProblemTime; /* 28h */
2776 U32 DiscoveryStatus; /* 14h */
2822 U32 PhyInfo; /* 14h */
2823 U32 AttachedDeviceInfo; /* 18h */
2831 U32 Reserved4; /* 24h */
2875 U32 DeviceInfo; /* 1Ch */
2922 U32 Reserved1; /* 08h */
2924 U32 Reserved2; /* 14h */
2939 U32 EnclosureMapping; /* 10h */
2967 U32 AttachedDeviceInfo; /* 18h */
2972 U32 PhyInfo; /* 20h */
3024 U32 Reserved1; /* 08h */
3025 U32 InvalidDwordCount; /* 0Ch */
3026 U32 RunningDisparityErrorCount; /* 10h */
3027 U32 LossDwordSynchCount; /* 14h */
3028 U32 PhyResetProblemCount; /* 18h */
3042 U32 Reserved1; /* 08h */
3052 U32 Reserved2; /* 20h */
3053 U32 Reserved3; /* 24h */
3087 U32 TimeStamp; /* 00h */
3088 U32 Reserved1; /* 04h */
3102 U32 Reserved1; /* 08h */
3103 U32 Reserved2; /* 0Ch */