Lines Matching refs:saa711x_write
104 static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value)
159 if (saa711x_write(sd, reg, data) < 0)
736 saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
737 saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10);
738 saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
740 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
741 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1,
743 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2,
746 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff);
747 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff);
748 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f);
776 saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, ctrl->val);
780 saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, ctrl->val);
784 saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, ctrl->val);
788 saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, ctrl->val);
794 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val);
796 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val | 0x80);
841 saa711x_write(sd, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
843 saa711x_write(sd, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
854 saa711x_write(sd, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
856 saa711x_write(sd, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
865 saa711x_write(sd, R_D0_B_HORIZ_PRESCALING,
870 saa711x_write(sd, R_D8_B_HORIZ_LUMA_SCALING_INC,
872 saa711x_write(sd, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB,
876 saa711x_write(sd, R_DC_B_HORIZ_CHROMA_SCALING,
878 saa711x_write(sd, R_DD_B_HORIZ_CHROMA_SCALING_MSB,
885 saa711x_write(sd, R_D5_B_LUMA_CONTRAST_CNTL,
887 saa711x_write(sd, R_D6_B_CHROMA_SATURATION_CNTL,
891 saa711x_write(sd, R_E0_B_VERT_LUMA_SCALING_INC,
893 saa711x_write(sd, R_E1_B_VERT_LUMA_SCALING_INC_MSB,
896 saa711x_write(sd, R_E2_B_VERT_CHROMA_SCALING_INC,
898 saa711x_write(sd, R_E3_B_VERT_CHROMA_SCALING_INC_MSB,
904 saa711x_write(sd, R_80_GLOBAL_CNTL_1,
960 saa711x_write(sd, R_0E_CHROMA_CNTL_1, reg);
1041 saa711x_write(sd, i - 2 + R_41_LCR_BASE, lcr[i]);
1228 saa711x_write(sd, R_10_CHROMA_CNTL_2,
1231 saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL,
1237 saa711x_write(sd, R_02_INPUT_CNTL_1,
1242 saa711x_write(sd, R_09_LUMA_CNTL,
1249 saa711x_write(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK,
1262 saa711x_write(sd, 0x11, (saa711x_read(sd, 0x11) & 0x7f) |
1279 saa711x_write(sd, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, state->enable);
1399 saa711x_write(sd, reg->reg & 0xff, reg->val & 0xff);