Lines Matching refs:reg_w
62 static int reg_w(struct sd *sd, __u16 index, __u16 value);
96 /* We don't use reg_w here, as that would cause all writes when
150 ret += reg_w(sd, 0x39, 0x0010); /* JPEG clock enable */
155 ret += reg_w(sd, 0x40+i, a);
156 ret += reg_w(sd, 0x60+i, b);
158 ret += reg_w(sd, 0x39, 0x0012); /* JPEG encoder enable */
363 ret += reg_w(sd, 0x00, 0xff00); /* power-down */
364 ret += reg_w(sd, 0x00, 0xbf17); /* reset everything */
365 ret += reg_w(sd, 0x00, 0xbf10); /* normal operation */
366 ret += reg_w(sd, 0x01, 0x0010); /* serial bus, SDS high */
367 ret += reg_w(sd, 0x01, 0x0000); /* serial bus, SDS low */
368 ret += reg_w(sd, 0x01, 0x0010); /* ..high 'beep-beep' */
369 ret += reg_w(sd, 0x01, 0x0030); /* Set sda scl to FSB mode */
390 ret += reg_w(sd, 0x00, 0xff00); /* power off */
391 ret += reg_w(sd, 0x00, 0xbf10); /* power on */
393 ret += reg_w(sd, 0x03, 0x405d); /* DRAM timings */
394 ret += reg_w(sd, 0x04, 0x0030); /* SDRAM timings */
396 ret += reg_w(sd, 0x20, y0 & 0xffff); /* Y buf.0, low */
397 ret += reg_w(sd, 0x21, y0 >> 16); /* Y buf.0, high */
398 ret += reg_w(sd, 0x24, u0 & 0xffff); /* U buf.0, low */
399 ret += reg_w(sd, 0x25, u0 >> 16); /* U buf.0, high */
400 ret += reg_w(sd, 0x28, v0 & 0xffff); /* V buf.0, low */
401 ret += reg_w(sd, 0x29, v0 >> 16); /* V buf.0, high */
403 ret += reg_w(sd, 0x22, y1 & 0xffff); /* Y buf.1, low */
404 ret += reg_w(sd, 0x23, y1 >> 16); /* Y buf.1, high */
405 ret += reg_w(sd, 0x26, u1 & 0xffff); /* U buf.1, low */
406 ret += reg_w(sd, 0x27, u1 >> 16); /* U buf.1, high */
407 ret += reg_w(sd, 0x2a, v1 & 0xffff); /* V buf.1, low */
408 ret += reg_w(sd, 0x2b, v1 >> 16); /* V buf.1, high */
410 ret += reg_w(sd, 0x32, y1 & 0xffff); /* JPEG buf 0 low */
411 ret += reg_w(sd, 0x33, y1 >> 16); /* JPEG buf 0 high */
413 ret += reg_w(sd, 0x34, y1 & 0xffff); /* JPEG buf 1 low */
414 ret += reg_w(sd, 0x35, y1 >> 16); /* JPEG bug 1 high */
416 ret += reg_w(sd, 0x36, 0x0000);/* JPEG restart interval */
417 ret += reg_w(sd, 0x37, 0x0804);/*JPEG VLE FIFO threshold*/
418 ret += reg_w(sd, 0x38, 0x0000);/* disable hw up-scaling */
419 ret += reg_w(sd, 0x3f, 0x0000); /* JPEG/MCTL test data */
467 ret += reg_w(sd, 0x10, start_cropx + x);
468 ret += reg_w(sd, 0x11, start_cropy + y);
469 ret += reg_w(sd, 0x12, start_cropx + x + cw);
470 ret += reg_w(sd, 0x13, start_cropy + y + ch);
481 ret += reg_w(sd, 0x14, sd->gspca_dev.width);
482 ret += reg_w(sd, 0x15, sd->gspca_dev.height);
485 ret += reg_w(sd, 0x30, sd->gspca_dev.width);
486 ret += reg_w(sd, 0x31, sd->gspca_dev.height);
491 ret += reg_w(sd, 0x2c, sd->gspca_dev.width/2);
492 ret += reg_w(sd, 0x2d, sd->gspca_dev.width/4);
494 ret += reg_w(sd, 0x2c, sd->gspca_dev.width);
496 ret += reg_w(sd, 0x00, 0xbf17); /* reset everything */
497 ret += reg_w(sd, 0x00, 0xbf10); /* normal operation */
501 ret += reg_w(sd, 0x3d, val & 0xffff); /* low bits */
502 ret += reg_w(sd, 0x3e, val >> 16); /* high bits */
541 ret += reg_w(sd, 0x16, val);
551 reg_w(sd, 0x39, 0x0000); /* disable JPEG encoder */
552 reg_w(sd, 0x16, 0x0000); /* stop video capture */