Lines Matching refs:oper_cfg
109 static struct vpss_oper_config oper_cfg;
114 return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
119 __raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
124 return __raw_readl(oper_cfg.vpss_regs_base1 + offset);
129 __raw_writel(val, oper_cfg.vpss_regs_base1 + offset);
135 return __raw_readl(oper_cfg.vpss_regs_base0 + offset);
141 __raw_writel(val, oper_cfg.vpss_regs_base0 + offset);
163 if (!oper_cfg.hw_ops.select_ccdc_source)
166 oper_cfg.hw_ops.select_ccdc_source(src_sel);
188 if (!oper_cfg.hw_ops.clear_wbl_overflow)
191 return oper_cfg.hw_ops.clear_wbl_overflow(wbl_sel);
232 spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
240 spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
316 spin_lock_irqsave(&oper_cfg.vpss_lock, flags);
325 spin_unlock_irqrestore(&oper_cfg.vpss_lock, flags);
332 if (!oper_cfg.hw_ops.enable_clock)
335 return oper_cfg.hw_ops.enable_clock(clock_sel, en);
373 oper_cfg.platform = DM355;
375 oper_cfg.platform = DM365;
377 oper_cfg.platform = DM644X;
393 oper_cfg.vpss_regs_base0 = ioremap(r1->start, resource_size(r1));
394 if (!oper_cfg.vpss_regs_base0) {
399 if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) {
411 oper_cfg.vpss_regs_base1 = ioremap(r2->start,
413 if (!oper_cfg.vpss_regs_base1) {
419 if (oper_cfg.platform == DM355) {
420 oper_cfg.hw_ops.enable_clock = dm355_enable_clock;
421 oper_cfg.hw_ops.select_ccdc_source = dm355_select_ccdc_source;
425 } else if (oper_cfg.platform == DM365) {
426 oper_cfg.hw_ops.enable_clock = dm365_enable_clock;
427 oper_cfg.hw_ops.select_ccdc_source = dm365_select_ccdc_source;
433 oper_cfg.hw_ops.clear_wbl_overflow = dm644x_clear_wbl_overflow;
435 spin_lock_init(&oper_cfg.vpss_lock);
442 iounmap(oper_cfg.vpss_regs_base0);
452 iounmap(oper_cfg.vpss_regs_base0);
455 if (oper_cfg.platform == DM355 || oper_cfg.platform == DM365) {
456 iounmap(oper_cfg.vpss_regs_base1);