Lines Matching refs:divider
137 * Note the largest clock divider value of 0xffff corresponds to:
158 static inline unsigned int clock_divider_to_ns(unsigned int divider)
161 return DIV_ROUND_CLOSEST((divider + 1) * 1000,
171 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
173 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16);
183 static inline unsigned int clock_divider_to_freq(unsigned int divider,
187 (divider + 1) * rollovers);
228 static u32 clock_divider_to_resolution(u16 divider)
235 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
239 static u64 pulse_width_count_to_ns(u16 count, u16 divider)
248 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
255 static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
264 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
275 * significant part and (up to) 16 bit clock divider count as a modulus.
276 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
402 u16 *divider)
404 *divider = carrier_freq_to_clock_divider(freq);
405 cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
406 return clock_divider_to_carrier_freq(*divider);
411 u16 *divider)
413 *divider = carrier_freq_to_clock_divider(freq);
414 cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
415 return clock_divider_to_carrier_freq(*divider);
419 u16 *divider)
426 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
427 cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
428 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
432 u16 *divider)
439 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
440 cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
441 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
642 u16 divider;
651 divider = (u16) atomic_read(&ir_state->rxclk_divider);
679 (u16) (p->hw_fifo_data & FIFO_RXTX), divider);