Lines Matching refs:status
66 int status;
69 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
72 return status;
77 int status = 0;
84 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
85 if (status < 0)
86 return status;
88 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
89 if (status < 0)
90 return status;
94 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
95 if (status < 0)
96 return status;
98 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
99 if (status < 0)
100 return status;
104 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
105 if (status < 0) {
111 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
113 if (status < 0) {
122 status = -1;
127 if (status < 0)
128 return status;
131 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
132 if (status < 0)
133 return status;
138 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
140 return status;
145 int status = 0;
148 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
149 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
150 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
153 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
156 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
157 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
158 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
161 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
162 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
163 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
167 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
168 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
169 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
172 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
173 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
174 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
177 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
179 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
181 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
185 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
186 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
187 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
189 return status;
195 int status = 0;
197 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
199 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
201 return status;
218 int status = 0;
222 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
226 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
230 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
234 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
240 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
244 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
247 return status;
252 int status = 0;
260 status = cx231xx_afe_setup_AFE_for_baseband(dev);
275 status = cx231xx_afe_adjust_ref_count(dev,
280 return status;
287 int status = 0;
295 status = afe_write_byte(dev, SUP_BLK_PWRDN,
298 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
300 if (status < 0)
304 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
306 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
308 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
311 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
313 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
315 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
318 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
323 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
328 status = afe_write_byte(dev, SUP_BLK_PWRDN,
331 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
333 if (status < 0)
337 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
339 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
341 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
345 status = -1;
352 status = afe_write_byte(dev, SUP_BLK_PWRDN,
355 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
357 if (status < 0)
361 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
363 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
365 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
368 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
370 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
372 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
375 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
380 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
385 status = afe_write_byte(dev, SUP_BLK_PWRDN,
388 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
390 if (status < 0)
394 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
396 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
398 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
402 status = -1;
406 return status;
413 int status = 0;
418 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
419 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
422 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
423 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
446 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
448 return status;
462 int status;
465 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
468 return status;
485 int status = 0;
493 status = cx231xx_set_power_mode(dev,
495 if (status < 0) {
498 __func__, status);
499 return status;
502 status = cx231xx_set_decoder_video_input(dev,
511 status = cx231xx_set_power_mode(dev,
513 if (status < 0) {
516 __func__, status);
517 return status;
520 status = cx231xx_set_decoder_video_input(dev,
533 return status;
539 int status = 0;
543 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
544 if (status < 0) {
547 __func__, status);
548 return status;
553 status = cx231xx_afe_set_input_mux(dev, input);
554 if (status < 0) {
557 __func__, status);
558 return status;
563 status = vid_blk_read_word(dev, AFE_CTRL, &value);
571 status = vid_blk_write_word(dev, AFE_CTRL, value);
573 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
575 status = vid_blk_write_word(dev, OUT_CTRL1, value);
578 status = cx231xx_read_modify_write_i2c_dword(dev,
585 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
586 if (status < 0) {
589 __func__, status);
590 return status;
594 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
603 status = vid_blk_write_word(dev, DFE_CTRL1, value);
606 status = cx231xx_read_modify_write_i2c_dword(dev,
612 status = cx231xx_read_modify_write_i2c_dword(dev,
620 status = vid_blk_read_word(dev, AFE_CTRL, &value);
627 status = vid_blk_write_word(dev, AFE_CTRL, value);
630 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
631 if (status < 0) {
634 __func__, status);
635 return status;
639 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
648 status = vid_blk_write_word(dev, DFE_CTRL1, value);
651 status = cx231xx_read_modify_write_i2c_dword(dev,
657 status = cx231xx_read_modify_write_i2c_dword(dev,
664 status = vid_blk_read_word(dev, AFE_CTRL, &value);
672 status = vid_blk_write_word(dev, AFE_CTRL, value);
674 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
684 status = vid_blk_read_word(dev, AFE_CTRL, &value);
692 status = vid_blk_write_word(dev, AFE_CTRL, value);
694 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
696 status = vid_blk_write_word(dev, OUT_CTRL1, value);
699 status = cx231xx_read_modify_write_i2c_dword(dev,
705 status = cx231xx_dif_set_standard(dev,
707 if (status < 0) {
710 __func__, status);
711 return status;
715 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
724 status = vid_blk_write_word(dev, DFE_CTRL1, value);
727 status = cx231xx_read_modify_write_i2c_dword(dev,
733 status = cx231xx_read_modify_write_i2c_dword(dev,
743 status = cx231xx_dif_set_standard(dev, dev->norm);
744 if (status < 0) {
747 __func__, status);
748 return status;
752 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
758 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
761 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
771 status = vid_blk_write_word(dev, DFE_CTRL1, value);
780 status = vid_blk_write_word(dev, DFE_CTRL1, value);
783 status = vid_blk_read_word(dev, PIN_CTRL, &value);
787 status = vid_blk_write_word(dev, PIN_CTRL, value);
790 status = cx231xx_read_modify_write_i2c_dword(dev,
796 status = cx231xx_read_modify_write_i2c_dword(dev,
802 status = cx231xx_read_modify_write_i2c_dword(dev,
813 status = vid_blk_read_word(dev, AFE_CTRL, &value);
817 status = vid_blk_write_word(dev, AFE_CTRL, value);
825 status = cx231xx_read_modify_write_i2c_dword(dev,
830 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
833 status = vid_blk_write_word(dev, OUT_CTRL1, value);
836 return status;
846 int status = 0;
852 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
859 status = cx231xx_read_modify_write_i2c_dword(dev,
863 status = cx231xx_read_modify_write_i2c_dword(dev,
868 status = cx231xx_read_modify_write_i2c_dword(dev,
874 status = cx231xx_read_modify_write_i2c_dword(dev,
882 status = cx231xx_read_modify_write_i2c_dword(dev,
887 status = cx231xx_read_modify_write_i2c_dword(dev,
895 status = cx231xx_read_modify_write_i2c_dword(dev,
900 status = cx231xx_read_modify_write_i2c_dword(dev,
908 return status;
913 int status = 0;
921 status = cx231xx_i2s_blk_set_audio_input(dev, input);
928 status = cx231xx_set_audio_decoder_input(dev, ainput);
930 return status;
937 int status;
942 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
944 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
951 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
956 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
958 status = vid_blk_write_word(dev, AC97_CTL,
962 status = vid_blk_write_word(dev, BAND_OUT_SEL,
969 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
972 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
973 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
977 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
978 status = vid_blk_write_word(dev, PATH1_SC_CTL,
986 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1002 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1009 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1013 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1017 status = cx231xx_read_modify_write_i2c_dword(dev,
1036 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1041 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1043 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1045 return status;
1052 int status = vid_blk_write_word(dev, HSCALE_CTRL, dev->hscale);
1053 if (status)
1054 return status;
1066 int status = 0;
1068 status = vid_blk_read_word(dev, PIN_CTRL, &value);
1070 status = vid_blk_write_word(dev, PIN_CTRL, value);
1072 return status;
1078 int status = 0;
1081 status = cx231xx_set_gpio_direction(dev,
1086 status = cx231xx_set_gpio_value(dev,
1090 return status;
1096 int status = 0;
1100 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1102 if (status < 0)
1103 return status;
1108 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1114 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1119 return status;
1129 int status = 0;
1134 status = cx231xx_reg_mask_write(dev,
1138 status = cx231xx_reg_mask_write(dev,
1142 status = cx231xx_reg_mask_write(dev,
1146 status = cx231xx_reg_mask_write(dev,
1152 status = cx231xx_reg_mask_write(dev,
1156 status = cx231xx_reg_mask_write(dev,
1161 status = cx231xx_reg_mask_write(dev,
1165 status = cx231xx_reg_mask_write(dev,
1169 status = cx231xx_reg_mask_write(dev,
1176 status = cx231xx_reg_mask_write(dev,
1180 status = cx231xx_reg_mask_write(dev,
1185 status = cx231xx_reg_mask_write(dev,
1189 status = cx231xx_reg_mask_write(dev,
1196 status = cx231xx_reg_mask_write(dev,
1200 status = cx231xx_reg_mask_write(dev,
1205 status = cx231xx_reg_mask_write(dev,
1209 status = cx231xx_reg_mask_write(dev,
1215 return status;
1220 int status = 0;
1226 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1239 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1245 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1246 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1249 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1252 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1254 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1256 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1258 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1260 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1262 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1264 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1266 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1268 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1271 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1274 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1277 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1280 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1282 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1285 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1288 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1291 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1297 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1299 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1301 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1303 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1305 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1307 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1309 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1311 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1313 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1316 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1319 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1322 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1325 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1327 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1330 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1333 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1336 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1343 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1344 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1345 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1346 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1347 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1348 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1350 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1352 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1354 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1356 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1357 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1359 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1361 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1363 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1370 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1371 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1372 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1373 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1374 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1375 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1377 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1379 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1381 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1383 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1385 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1387 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1389 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1391 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1400 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1402 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1404 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1406 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1408 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1410 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1412 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1414 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1416 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1419 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1422 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1425 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1427 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1430 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1433 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1436 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1438 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1447 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1449 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1451 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1453 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1455 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1457 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1459 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1461 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1463 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1466 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1469 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1472 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1474 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1477 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1480 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1483 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1485 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1503 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
1504 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
1505 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
1506 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1507 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
1508 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1510 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1512 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1514 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1516 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
1518 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1520 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1522 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1525 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
1526 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
1528 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
1535 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1537 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1539 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1541 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1543 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1545 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1547 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1549 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1551 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1554 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1557 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1560 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1563 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1565 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1568 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1571 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1574 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1592 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
1594 return status;
1599 int status = 0;
1603 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
1607 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
1609 return status;
1614 int status = 0;
1619 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
1628 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
1630 return status;
1638 int status = 0;
1641 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1645 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1648 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1651 return status;
1657 int status = 0;
1661 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1664 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1667 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1671 return status;
1677 int status = 0;
1681 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1683 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1693 return status;
1703 int status = 0;
1715 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1717 if (status < 0)
1718 return status;
1732 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1741 status =
1751 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1766 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1776 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1787 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1797 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1808 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1830 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1840 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1850 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1860 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1870 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1899 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1905 status = cx231xx_afe_update_power_control(dev, mode);
1908 status = cx231xx_i2s_blk_update_power_control(dev, mode);
1910 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1916 return status;
1923 int status = 0;
1925 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1927 if (status > 0)
1928 return status;
1937 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
1940 return status;
1950 int status = 0;
1953 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1955 if (status < 0)
1956 return status;
1965 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
1968 return status;
1975 int status = 0;
1978 status =
1980 if (status < 0)
1981 return status;
1990 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
1993 return status;
1998 int status = 0;
2004 status =
2010 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2015 status =
2021 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2026 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2027 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2032 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2033 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2037 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2040 return status;
2129 int status = 0;
2131 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2133 return status;
2138 int status = 0;
2140 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2142 return status;
2159 int status = 0;
2172 status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2177 return status;
2193 int status = 0;
2205 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2219 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2221 return status;
2229 int status = 0;
2237 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2238 if (status < 0)
2245 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2246 if (status < 0)
2253 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2254 if (status < 0)
2257 return status;
2262 int status = 0;
2271 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2272 if (status < 0)
2279 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2280 if (status < 0)
2288 status =
2290 if (status < 0)
2293 return status;
2298 int status = 0;
2310 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2315 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2320 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2326 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2331 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2336 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2340 return status;
2346 int status = 0;
2355 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2360 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2365 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2377 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2382 return status;
2387 int status = 0;
2398 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2402 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2418 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2423 status = 0;
2434 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2436 return status;
2441 int status = 0;
2445 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2450 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2454 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2458 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2462 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2464 return status;
2469 int status = 0;
2474 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2478 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2482 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2484 return status;
2495 int status = 0;
2502 status = cx231xx_gpio_i2c_start(dev);
2505 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
2508 status = cx231xx_gpio_i2c_read_ack(dev);
2514 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
2518 status = cx231xx_gpio_i2c_write_ack(dev);
2523 status = cx231xx_gpio_i2c_write_nak(dev);
2526 status = cx231xx_gpio_i2c_end(dev);
2531 return status;
2539 int status = 0;
2546 status = cx231xx_gpio_i2c_start(dev);
2549 status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
2552 status = cx231xx_gpio_i2c_read_ack(dev);
2556 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
2559 status = cx231xx_gpio_i2c_read_ack(dev);
2563 status = cx231xx_gpio_i2c_end(dev);