Lines Matching refs:cx18_write_reg
221 cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN);
266 cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
267 cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7,
270 cx18_write_reg(cx, 2, CX18_FAST_CLOCK_PLL_POST);
271 cx18_write_reg(cx, 1, CX18_FAST_CLOCK_PLL_PRESCALE);
272 cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
277 cx18_write_reg(cx, lowpwr ? 0xD : 0xC, CX18_SLOW_CLOCK_PLL_INT);
278 cx18_write_reg(cx, lowpwr ? 0x30C344 : 0x124927F,
280 cx18_write_reg(cx, 3, CX18_SLOW_CLOCK_PLL_POST);
284 cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT);
285 cx18_write_reg(cx, 0x2BE2FE, CX18_MPEG_CLOCK_PLL_FRAC);
286 cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST);
333 cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);
337 cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH);
338 cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1);
339 cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2);
344 cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);
345 cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);
354 cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG);
359 cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7);
360 cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR);
362 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02); /* AO */
363 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09); /* AI2 */
364 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05); /* VIM1 */
365 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06); /* AI1 */
366 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07); /* 3D comb */
367 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10); /* ME */
368 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12); /* ENC */
369 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13); /* PK */
370 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11); /* RC */
371 cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14); /* AVO */
381 cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK);