Lines Matching refs:ar_outl
55 #define ar_outl(val, addr) outl((unsigned long)(val), (unsigned long)(addr))
162 ar_outl(addr, PLDI2CDATA);
166 ar_outl(1, PLDI2CCND);
170 ar_outl(data1, PLDI2CDATA);
172 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
176 ar_outl(data2, PLDI2CDATA);
178 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
183 ar_outl(data3, PLDI2CDATA);
185 ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
192 ar_outl(2, PLDI2CCND);
193 ar_outl(2, PLDI2CCND);
208 ar_outl(0x0, PLDI2CCR); /* I2CCR Disable */
209 ar_outl(0x0300, PLDI2CMOD); /* I2CMOD ACK/8b-data/7b-addr/auto */
210 ar_outl(0x1, PLDI2CACK); /* I2CACK ACK */
215 ar_outl(369, PLDI2CFREQ); /* BCLK = 75MHz */
217 ar_outl(244, PLDI2CFREQ); /* BCLK = 50MHz */
219 ar_outl(244, PLDI2CFREQ); /* default: BCLK = 50MHz */
220 ar_outl(0x1, PLDI2CCR); /* I2CCR Enable */
231 ar_outl(0x8000, M32R_DMAEN_PORTL); /* disable DMA0 */
236 ar_outl(0x8080, M32R_DMAEN_PORTL); /* enable DMA0 */
241 ar_outl(0x8000, M32R_DMAEDET_PORTL); /* clear status */
291 ar_outl(0xa1871300, M32R_DMA0CR0_PORTL);
292 ar_outl(0x01000000, M32R_DMA0CR1_PORTL);
295 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL);
296 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL);
297 ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* destination addr. */
298 ar_outl(ar->line_buff, M32R_DMA0RDA_PORTL); /* reload address */
299 ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL); /* byte count (bytes) */
300 ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL); /* reload count (bytes) */
306 ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1);
317 ar_outl(arvcr1, ARVCR1);
319 ar_outl(0x8000, M32R_DMAEDET_PORTL);
320 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
321 ar_outl(0x01000000, M32R_DMA0CR1_PORTL);
322 ar_outl(ARDATA32, M32R_DMA0CSA_PORTL);
323 ar_outl(ARDATA32, M32R_DMA0RSA_PORTL);
324 ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL);
325 ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL);
337 ar_outl(virt_to_phys(ar->frame[l]), M32R_DMA0CDA_PORTL);
343 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
348 ar_outl(virt_to_phys(ar->frame[h]), M32R_DMA0CDA_PORTL);
354 ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
567 ar_outl(arvcr1, ARVCR1); /* disable */
595 ar_outl(0, ARVCR0); /* assert reset of AR LSI */
598 ar_outl(ARVCR0_RST, ARVCR0); /* negate reset of AR LSI (enable) */
603 ar_outl(ARINTSEL_INT3, ARINTSEL);
609 ar_outl(cr, ARVCR1);