Lines Matching refs:saa7146_write
1199 saa7146_write(budget->dev, MC1, MASK_20); /* DMA3 off */
1215 saa7146_write(budget->dev, MC1, (MASK_04 | MASK_20)); /* DMA3 on */
2363 saa7146_write(dev, MC1, MASK_31);
2369 saa7146_write(dev, DD1_STREAM_B, 0);
2371 saa7146_write(dev, DD1_INIT, 0x00000200);
2372 saa7146_write(dev, BRS_CTRL, 0x00000000); // VBI
2373 saa7146_write(dev, MC2,
2385 saa7146_write(dev, MC1, MASK_29);
2387 saa7146_write(dev, RPS_TOV1, 0);
2406 saa7146_write(dev, EC1SSR, (0x03<<2) | 3 );
2408 saa7146_write(dev, ECT1R, 0x3fff );
2411 saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
2413 saa7146_write(dev, MC1, (MASK_13 | MASK_29 ));
2427 saa7146_write(dev, MC1, ( MASK_29 ));
2455 saa7146_write(dev, GPIO_CTRL, 0x500000);
2489 saa7146_write(dev, DD1_STREAM_B, 0x00000000);
2490 saa7146_write(dev, MC2, (MASK_10 | MASK_26));
2492 saa7146_write(dev, DD1_INIT, 0x00000600);
2493 saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
2495 saa7146_write(dev, BRS_CTRL, 0x60000000);
2496 saa7146_write(dev, MC2, MASK_08 | MASK_24);
2499 saa7146_write(dev, PCI_BT_V1, 0x001c0000 | (saa7146_read(dev, PCI_BT_V1) & ~0x001f0000));
2500 saa7146_write(dev, BASE_ODD3, 0);
2501 saa7146_write(dev, BASE_EVEN3, 0);
2502 saa7146_write(dev, PROT_ADDR3, TS_WIDTH * TS_HEIGHT);
2503 saa7146_write(dev, PITCH3, TS_WIDTH);
2504 saa7146_write(dev, BASE_PAGE3, av7110->pt.dma | ME1 | 0x90);
2505 saa7146_write(dev, NUM_LINE_BYTE3, (TS_HEIGHT << 16) | TS_WIDTH);
2506 saa7146_write(dev, MC2, MASK_04 | MASK_20);
2517 saa7146_write(dev, PCI_BT_V1, 0x1c1f101f);
2518 saa7146_write(dev, BCS_CTRL, 0x80400040);
2520 saa7146_write(dev, DD1_STREAM_B, 0x00000000);
2521 saa7146_write(dev, DD1_INIT, 0x03000200);
2522 saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
2523 saa7146_write(dev, BRS_CTRL, 0x60000000);
2524 saa7146_write(dev, BASE_ODD3, 0);
2525 saa7146_write(dev, BASE_EVEN3, 0);
2526 saa7146_write(dev, PROT_ADDR3, TS_WIDTH * TS_HEIGHT);
2527 saa7146_write(dev, BASE_PAGE3, av7110->pt.dma | ME1 | 0x90);
2529 saa7146_write(dev, PITCH3, TS_WIDTH);
2530 saa7146_write(dev, NUM_LINE_BYTE3, (TS_HEIGHT << 16) | TS_WIDTH);
2533 saa7146_write(dev, MC2, 0x077c077c);
2534 saa7146_write(dev, GPIO_CTRL, 0x000000);
2540 saa7146_write(dev, EC1SSR, (0x03<<2) | 3 );
2542 saa7146_write(dev, ECT1R, 0x3fff );
2574 saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
2583 saa7146_write(dev, RPS_THRESH1, (TS_HEIGHT*1) | MASK_12 );
2586 saa7146_write(dev, MC1, (MASK_13 | MASK_29));
2591 saa7146_write(dev, PCI_BT_V1, 0x1c00101f);
2592 saa7146_write(dev, BCS_CTRL, 0x80400040);
2595 saa7146_write(dev, DD1_STREAM_B, 0x00000000);
2596 saa7146_write(dev, DD1_INIT, 0x03000000);
2597 saa7146_write(dev, MC2, (MASK_09 | MASK_25 | MASK_10 | MASK_26));
2600 saa7146_write(dev, MC2, 0x077c077c);
2601 saa7146_write(dev, GPIO_CTRL, 0x000000);
2739 saa7146_write(saa, MC1, MASK_29);
2743 saa7146_write(saa, MC1, MASK_20); /* DMA3 off */