Lines Matching refs:tda1004x_write_mask
173 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
214 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
223 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
374 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
406 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
407 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
408 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
496 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
500 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f);
507 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0);
555 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
622 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
625 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
626 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
627 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
628 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
629 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
630 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
633 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
634 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
637 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
653 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
660 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
664 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
668 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00); // set AGC polarities
674 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities
678 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40);
679 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
681 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80);
682 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10,
686 tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on
695 // tda1004x_write_mask(state, 0x50, 0x80, 0x80); // handle out of guard echoes
711 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
712 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
713 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
716 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
739 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto
740 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
741 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
742 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
744 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto
750 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
756 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
761 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
765 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
769 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
779 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
783 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
787 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
791 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
816 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
820 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
830 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
831 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
835 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
836 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
840 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
841 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
845 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
846 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
850 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
851 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
861 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
862 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
866 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
867 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
871 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
872 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
882 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
883 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
887 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
889 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1);
1136 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1137 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1138 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1187 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1196 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f,
1199 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0);
1200 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);