Lines Matching refs:tda1004x_write_byteI
128 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
189 return tda1004x_write_byteI(state, reg, val);
201 result = tda1004x_write_byteI(state, reg + i, buf[i]);
250 tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
281 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a);
282 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab);
294 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
295 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
307 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
308 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55);
329 tda1004x_write_byteI(state, dspCodeCounterReg, 0);
375 tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
438 tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0);
441 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8
444 tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3
448 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
451 tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3
454 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67);
456 tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72);
460 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c);
461 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00);
464 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d);
465 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7);
468 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
469 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59);
472 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7);
473 tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f);
494 tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
499 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0x33);
526 tda1004x_write_byteI(state, TDA1004X_CONFC4, 4);
528 tda1004x_write_byteI(state, TDA1004X_CONFC4, confc4);
608 return tda1004x_write_byteI(state, buf[0], buf[1]);
631 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
632 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
635 tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
654 tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream
655 tda1004x_write_byteI(state, TDA1004X_CONFC1, 0x88); // enable pulse killer
659 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup
663 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
667 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x0a); // AGC setup
671 tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup
672 tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold
673 tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize
685 tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38);
687 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // }
688 tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
689 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // }
690 tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // }
691 tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1
692 tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits
693 tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
694 tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config
1192 tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0xff);