Lines Matching defs:stb0899_write_reg
542 int stb0899_write_reg(struct stb0899_state *state, unsigned int reg, u8 data)
578 stb0899_write_reg(state, STB0899_NCOARSE, mdiv);
593 stb0899_write_reg(state, postproc[ctl].gpio, 0x02);
595 stb0899_write_reg(state, postproc[ctl].gpio, 0x82);
598 stb0899_write_reg(state, postproc[ctl].gpio, 0x82);
600 stb0899_write_reg(state, postproc[ctl].gpio, 0x02);
706 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
712 stb0899_write_reg(state, STB0899_DISFIFO, cmd->msg[i]);
716 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
800 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
804 stb0899_write_reg(state, STB0899_DISFIFO, 0x00);
808 stb0899_write_reg(state, STB0899_DISFIFO, 0xff);
813 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
819 stb0899_write_reg(state, STB0899_DISCNTRL1, old_state);
837 stb0899_write_reg(state, STB0899_DISCNTRL2, reg);
842 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
846 stb0899_write_reg(state, STB0899_DISCNTRL1, reg);
850 stb0899_write_reg(state, STB0899_DISF22, f22_tx); /* DiSEqC Tx freq */
875 if ((rc = stb0899_write_reg(state, STB0899_SYNTCTRL, STB0899_SELOSCI)))
878 if ((rc = stb0899_write_reg(state, STB0899_STOPCLK1, 0x00)))
880 if ((rc = stb0899_write_reg(state, STB0899_STOPCLK2, 0x00)))
900 stb0899_write_reg(state, config->init_dev[i].address, config->init_dev[i].data);
913 stb0899_write_reg(state, config->init_s1_demod[i].address, config->init_s1_demod[i].data);
926 stb0899_write_reg(state, config->init_tst[i].address, config->init_tst[i].data);
1190 stb0899_write_reg(state, STB0899_GPIO00CFG, 0x82);
1191 stb0899_write_reg(state, STB0899_GPIO01CFG, 0x02);
1192 stb0899_write_reg(state, STB0899_GPIO02CFG, 0x00);
1195 stb0899_write_reg(state, STB0899_GPIO00CFG, 0x02);
1196 stb0899_write_reg(state, STB0899_GPIO01CFG, 0x02);
1197 stb0899_write_reg(state, STB0899_GPIO02CFG, 0x82);
1200 stb0899_write_reg(state, STB0899_GPIO00CFG, 0x82);
1201 stb0899_write_reg(state, STB0899_GPIO01CFG, 0x82);
1202 stb0899_write_reg(state, STB0899_GPIO02CFG, 0x82);
1226 stb0899_write_reg(state, STB0899_DISEQCOCFG, 0x66);
1229 stb0899_write_reg(state, STB0899_ACRPRESC, reg);
1230 stb0899_write_reg(state, STB0899_ACRDIV1, div);
1233 stb0899_write_reg(state, STB0899_DISEQCOCFG, 0x20);
1253 if (stb0899_write_reg(state, STB0899_I2CRPT, i2c_stat) < 0)
1258 if (stb0899_write_reg(state, STB0899_I2CRPT, i2c_stat) < 0)
1324 stb0899_write_reg(state, STB0899_FECM, reg);
1326 stb0899_write_reg(state, STB0899_RSULC, 0xb1);
1327 stb0899_write_reg(state, STB0899_TSULC, 0x40);
1328 stb0899_write_reg(state, STB0899_RSLLC, 0x42);
1329 stb0899_write_reg(state, STB0899_TSLPL, 0x12);
1333 stb0899_write_reg(state, STB0899_TSTRES, reg);
1352 stb0899_write_reg(state, STB0899_FECM, reg);
1354 stb0899_write_reg(state, STB0899_RSULC, 0xb1);
1355 stb0899_write_reg(state, STB0899_TSULC, 0x42);
1356 stb0899_write_reg(state, STB0899_RSLLC, 0x40);
1357 stb0899_write_reg(state, STB0899_TSLPL, 0x02);
1361 stb0899_write_reg(state, STB0899_TSTRES, reg);
1380 stb0899_write_reg(state, STB0899_FECM, reg);
1382 stb0899_write_reg(state, STB0899_RSULC, 0xa1);
1383 stb0899_write_reg(state, STB0899_TSULC, 0x61);
1384 stb0899_write_reg(state, STB0899_RSLLC, 0x42);
1388 stb0899_write_reg(state, STB0899_TSTRES, reg);
1499 stb0899_write_reg(state, STB0899_AGCRFCFG, 0x11);
1508 // stb0899_write_reg(state, STB0899_ERRCTRL1, 0x3d); /* Viterbi Errors */
1540 stb0899_write_reg(state, STB0899_AGCRFCFG, 0x1c);
1552 // stb0899_write_reg(state, STB0899_ERRCTRL1, 0xb6); /* Packet Errors */