Lines Matching defs:config
51 struct drx397xD_config config;
195 .addr = s->config.demod_address,
246 .addr = s->config.demod_address,
251 .addr = s->config.demod_address,
273 .addr = s->config.demod_address,
395 WR16(s, 0x420034, s->config.w50); /* code 4, log 4 */
396 WR16(s, 0x420035, s->config.w52); /* code 15, log 9 */
397 WR16(s, 0x420036, s->config.demod_address << 1);
398 WR16(s, 0x420037, s->config.w56); /* code (set_i2c ?? initX 1 ), log 1 */
400 if ((s->config.w56 & 8) == 0)
493 s->config.w9C &= ~2;
494 EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
503 s->config.w9C &= ~2;
504 EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
514 s->config.w9C |= 2;
515 EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
541 if (s->config.d60 != 2)
561 if (s->config.d5C == 0) {
564 s->config.d5C = 1;
567 if (s->config.d5C != 1)
599 clk_limit = s->config.f_osc * MAX_CLOCK_DRIFT / 1000;
601 if (clk - s->config.f_osc * 1000 + clk_limit <= 2 * clk_limit) {
604 s->config.f_osc * 1000, clk - s->config.f_osc * 1000);
618 si = s->config.wA0;
619 if (s->config.w98 == 0) {
626 if (s->config.w9A == 0)
652 pr_debug("%s %d\n", __func__, s->config.d60);
654 if (s->config.d60 != 2)
660 s->config.d60 = 1;
707 rc = SetCfgIfAgc(s, &s->config.ifagc);
711 rc = SetCfgRfAgc(s, &s->config.rfagc);
953 if (s->config.s20d24 == 1) {
1038 ebx = div64_u64(((u64) (s->config.f_if + df_tuner) << 28) +
1072 s->config.d60 = 2;
1089 s->config.rfagc.d00 = 2; /* 0x7c */
1090 s->config.rfagc.w04 = 0;
1091 s->config.rfagc.w06 = 0x3ff;
1093 s->config.ifagc.d00 = 0; /* 0x68 */
1094 s->config.ifagc.w04 = 0;
1095 s->config.ifagc.w06 = 140;
1096 s->config.ifagc.w08 = 0;
1097 s->config.ifagc.w0A = 0x3ff;
1098 s->config.ifagc.w0C = 0x388;
1101 s->config.ss76 = 820;
1102 s->config.ss78 = 2200;
1103 s->config.ss7A = 150;
1106 s->config.w50 = 4;
1107 s->config.w52 = 9;
1109 s->config.f_if = 42800000; /* d14: intermediate frequency [Hz] */
1110 s->config.f_osc = 48000; /* s66 : oscillator frequency [kHz] */
1111 s->config.w92 = 12000;
1113 s->config.w9C = 0x000e;
1114 s->config.w9E = 0x0000;
1117 s->config.wA0 = 4;
1118 s->config.w98 = 1;
1119 s->config.w9A = 1;
1171 if (s->config.w92 > 20000 || s->config.w92 % 4000) {
1183 rc = WR16(s, 0x2410012, s->config.w92 / 4000);
1195 s->f_osc = s->config.f_osc * 1000; /* initial estimator */
1197 s->config.w56 = 1;
1229 s->config.w9C = 0x0e;
1231 s->config.w9C = 0;
1272 rc = WR16(s, 0x0C20013, s->config.w9E);
1275 rc = WR16(s, 0x0C20015, s->config.w9C);
1301 rc = SetCfgIfAgc(s, &s->config.ifagc);
1305 rc = SetCfgRfAgc(s, &s->config.rfagc);
1313 s->config.d5C = 0;
1314 s->config.d60 = 1;
1315 s->config.d48 = 1;
1332 s->config.s20d24 = 1;
1386 if (s->config.ifagc.d00 == 2) {
1477 struct dvb_frontend *drx397xD_attach(const struct drx397xD_config *config,
1489 memcpy(&state->config, config, sizeof(struct drx397xD_config));