Lines Matching refs:dib7000m_write_word
80 static int dib7000m_write_word(struct dib7000m_state *state, u16 reg, u16 val)
103 dib7000m_write_word(state, r, *n++);
154 ret |= dib7000m_write_word(state, 294 + state->reg_offs, smo_mode);
155 ret |= dib7000m_write_word(state, 295 + state->reg_offs, fifo_threshold); /* synchronous fread */
156 ret |= dib7000m_write_word(state, 1795, outreg);
157 ret |= dib7000m_write_word(state, 1805, sram);
163 dib7000m_write_word(state, 909, clk_cfg1);
214 dib7000m_write_word(state, 903 + offset, reg_903);
215 dib7000m_write_word(state, 904 + offset, reg_904);
216 dib7000m_write_word(state, 905 + offset, reg_905);
217 dib7000m_write_word(state, 906 + offset, reg_906);
229 ret |= dib7000m_write_word(state, 914, reg_914);
240 dib7000m_write_word(state, 913, 0);
241 dib7000m_write_word(state, 914, reg_914 & 0x3);
243 dib7000m_write_word(state, 913, (1 << 15));
244 dib7000m_write_word(state, 914, reg_914 & 0x3);
269 ret |= dib7000m_write_word(state, 913, reg_913);
270 ret |= dib7000m_write_word(state, 914, reg_914);
292 dib7000m_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
293 dib7000m_write_word(state, 24, (u16) ((timf ) & 0xffff));
309 dib7000m_write_word(state, 263 + state->reg_offs, 6);
310 dib7000m_write_word(state, 264 + state->reg_offs, 6);
311 dib7000m_write_word(state, 266 + state->reg_offs, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
313 dib7000m_write_word(state, 263 + state->reg_offs, 1);
314 dib7000m_write_word(state, 264 + state->reg_offs, 0);
315 dib7000m_write_word(state, 266 + state->reg_offs, 0);
325 // dib7000m_write_word(state, 928, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SAD is writting in set_bandwidth
326 dib7000m_write_word(state, 929, (0 << 1) | (0 << 0));
327 dib7000m_write_word(state, 930, 776); // 0.625*3.3 / 4096
330 dib7000m_write_word(state, 929, (1 << 0));
331 dib7000m_write_word(state, 929, (0 << 0));
340 dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff));
341 dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff));
342 dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff));
343 dib7000m_write_word(state, 22, (u16) ( bw->ifreq & 0xffff));
345 dib7000m_write_word(state, 928, bw->sad_cfg);
374 dib7000m_write_word(state, 910, reg_910); // pll cfg
375 dib7000m_write_word(state, 907, reg_907); // clk cfg0
376 dib7000m_write_word(state, 908, 0x0006); // clk_cfg1
387 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0));
390 //dib7000m_write_word(state, 908, (1 << 14) | (3 << 12) |(0 << 11) |
394 dib7000m_write_word(state, 908, clk_cfg1);
396 dib7000m_write_word(state, 908, clk_cfg1);
399 dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7));
407 dib7000m_write_word(st, 773, st->cfg.gpio_dir);
408 dib7000m_write_word(st, 774, st->cfg.gpio_val);
412 dib7000m_write_word(st, 775, st->cfg.gpio_pwm_pos);
414 dib7000m_write_word(st, 780, st->cfg.pwm_freq_div);
527 dib7000m_write_word(state, 898, 0xffff);
528 dib7000m_write_word(state, 899, 0xffff);
529 dib7000m_write_word(state, 900, 0xff0f);
530 dib7000m_write_word(state, 901, 0xfffc);
532 dib7000m_write_word(state, 898, 0);
533 dib7000m_write_word(state, 899, 0);
534 dib7000m_write_word(state, 900, 0);
535 dib7000m_write_word(state, 901, 0);
549 dib7000m_write_word(state, 1794, dib7000m_read_word(state, 1794) & ~(1 << 1) );
558 dib7000m_write_word(state, 1796, 0x0); // select DVB-T output
561 dib7000m_write_word(state, 261 + state->reg_offs, 2);
563 dib7000m_write_word(state, 224 + state->reg_offs, 1);
567 dib7000m_write_word(state, 36, 0x0755);
569 dib7000m_write_word(state, 36, 0x1f55);
573 dib7000m_write_word(state, 909, (3 << 10) | (1 << 6));
575 dib7000m_write_word(state, 909, (3 << 4) | 1);
590 dib7000m_write_word(state, 898, 0x0c00);
591 dib7000m_write_word(state, 898, 0x0000);
616 return dib7000m_write_word(state, 103, (dib7000m_read_word(state, 103) & 0xff00) | split_offset);
657 dib7000m_write_word(state, 72 , agc->setup);
658 dib7000m_write_word(state, 73 , agc->inv_gain);
659 dib7000m_write_word(state, 74 , agc->time_stabiliz);
660 dib7000m_write_word(state, 97 , (agc->alpha_level << 12) | agc->thlock);
663 dib7000m_write_word(state, 98, (agc->alpha_mant << 5) | agc->alpha_exp);
664 dib7000m_write_word(state, 99, (agc->beta_mant << 6) | agc->beta_exp);
671 dib7000m_write_word(state, 102, state->wbd_ref);
673 dib7000m_write_word(state, 102, agc->wbd_ref);
675 dib7000m_write_word(state, 103, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8) );
676 dib7000m_write_word(state, 104, agc->agc1_max);
677 dib7000m_write_word(state, 105, agc->agc1_min);
678 dib7000m_write_word(state, 106, agc->agc2_max);
679 dib7000m_write_word(state, 107, agc->agc2_min);
680 dib7000m_write_word(state, 108, (agc->agc1_pt1 << 8) | agc->agc1_pt2 );
681 dib7000m_write_word(state, 109, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
682 dib7000m_write_word(state, 110, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
683 dib7000m_write_word(state, 111, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
686 dib7000m_write_word(state, 71, agc->agc1_pt3);
689 dib7000m_write_word(state, 929, (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2));
694 dib7000m_write_word(state, 88 + i, b[i]);
703 dib7000m_write_word(state, 23, (u16) (timf >> 16));
704 dib7000m_write_word(state, 24, (u16) (timf & 0xffff));
734 dib7000m_write_word(state, 75, 32768);
737 dib7000m_write_word(state, 103, 1 << 8); /* force 0 split on WBD and restart AGC */
751 dib7000m_write_word(state, 72, cfg_72 | (1 << 4)); /* freeze AGC loop */
752 dib7000m_write_word(state, 103, 2 << 9); /* fast split search 0.25kHz */
759 dib7000m_write_word(state, 75, dib7000m_read_word(state, 390)); /* set AGC gain start value */
761 dib7000m_write_word(state, 72, cfg_72 & ~(1 << 4)); /* std AGC loop */
762 dib7000m_write_word(state, 103, (state->current_agc->wbd_alpha << 9) | agc_split); /* standard split search */
831 dib7000m_write_word(state, 0, value);
832 dib7000m_write_word(state, 5, (seq << 4));
850 dib7000m_write_word(state, 267 + state->reg_offs, value);
855 dib7000m_write_word(state, 26, (6 << 12) | (6 << 8) | 0x80);
858 dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (1 << 9) | (3 << 5) | (1 << 4) | (0x3));
861 dib7000m_write_word(state, 32, (0 << 4) | 0x3);
864 dib7000m_write_word(state, 33, (0 << 4) | 0x5);
912 dib7000m_write_word(state, 214 + value + state->reg_offs, est[value]);
944 ret |= dib7000m_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time
945 ret |= dib7000m_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time
947 ret |= dib7000m_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time
948 ret |= dib7000m_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time
950 ret |= dib7000m_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time
951 ret |= dib7000m_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time
955 ret |= dib7000m_write_word(state, 0, (u16) (value | (1 << 9)));
959 dib7000m_write_word(state, 1793, 0);
963 ret |= dib7000m_write_word(state, 0, (u16) value);
1006 ret |= dib7000m_write_word(state, 898, 0x4000);
1007 ret |= dib7000m_write_word(state, 898, 0x0000);
1012 ret |= dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3));
1027 ret |= dib7000m_write_word(state, 26, value);
1037 ret |= dib7000m_write_word(state, 32, value);
1047 ret |= dib7000m_write_word(state, 33, value);