Lines Matching refs:dib7000m_read_word
65 static u16 dib7000m_read_word(struct dib7000m_state *state, u16 reg)
118 smo_mode = (dib7000m_read_word(state, 294 + state->reg_offs) & 0x0010) | (1 << 1);
160 u16 clk_cfg1 = dib7000m_read_word(state, 909) & 0xfffd;
223 u16 reg_913 = dib7000m_read_word(state, 913),
224 reg_914 = dib7000m_read_word(state, 914);
549 dib7000m_write_word(state, 1794, dib7000m_read_word(state, 1794) & ~(1 << 1) );
602 agc = dib7000m_read_word(state, 390);
616 return dib7000m_write_word(state, 103, (dib7000m_read_word(state, 103) & 0xff00) | split_offset);
625 dyn_gain = dib7000m_read_word(state, 390);
688 // (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2), agc->wbd_inv, agc->wbd_sel);
689 dib7000m_write_word(state, 929, (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2));
701 u32 timf = (dib7000m_read_word(state, 436) << 16) | dib7000m_read_word(state, 437);
711 u16 cfg_72 = dib7000m_read_word(state, 72);
758 agc_split = (u8)dib7000m_read_word(state, 392); /* store the split value for the next time */
759 dib7000m_write_word(state, 75, dib7000m_read_word(state, 390)); /* set AGC gain start value */
954 value = dib7000m_read_word(state, 0);
961 dib7000m_read_word(state, 537);
970 u16 irq_pending = dib7000m_read_word(state, reg);
1050 if ((dib7000m_read_word(state, 535) >> 6) & 0x1)
1082 if ((value = dib7000m_read_word(state, 896)) != 0x01b3) {
1087 state->revision = dib7000m_read_word(state, 897);
1097 if (state->revision == 0x4000 && dib7000m_read_word(state, 769) == 0x4000) {
1117 u16 tps = dib7000m_read_word(state,480);
1166 /* native interleaver: (dib7000m_read_word(state, 481) >> 5) & 0x1 */
1222 u16 lock = dib7000m_read_word(state, 535);
1243 *ber = (dib7000m_read_word(state, 526) << 16) | dib7000m_read_word(state, 527);
1250 *unc = dib7000m_read_word(state, 534);
1257 u16 val = dib7000m_read_word(state, 390);