Lines Matching refs:dib0090_write_reg
163 static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
182 dib0090_write_reg(state, r++, *b++);
244 dib0090_write_reg(state, 0x24, EN_PLL);
245 dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
248 dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0);
250 dib0090_write_reg(state, 0x23,
258 dib0090_write_reg(state, 0x23,
266 dib0090_write_reg(state, 0x21,
291 dib0090_write_reg(state, 0x04, 0);
293 dib0090_write_reg(state, 0x04, 1);
541 dib0090_write_reg(state, gain_reg_addr[i], v);
561 dib0090_write_reg(state, 0x2a, 0xffff);
581 dib0090_write_reg(state, 0x33, 0xffff);
616 dib0090_write_reg(state, 0x32, (3 << 11));
618 dib0090_write_reg(state, 0x32, (0 << 11));
620 dib0090_write_reg(state, 0x39, (1 << 10));
637 dib0090_write_reg(state, 0x04, 0x0);
662 dib0090_write_reg(state, 0x32, 0);
663 dib0090_write_reg(state, 0x39, 0);
744 dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63)); /* cap value = 63 : narrow BB filter : Fc = 1.8MHz */
745 dib0090_write_reg(state, 0x04, 0x0);
749 dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32));
750 dib0090_write_reg(state, 0x04, 0x01); /*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fast */
876 dib0090_write_reg(state, r, pgm_read_word(n++));
887 dib0090_write_reg(state, 0x14, l);
904 dib0090_write_reg(state, 0x1f, 0x7);
912 dib0090_write_reg(state, 0x1f, 0x4);
959 dib0090_write_reg(state, state->dc->addr, *val);
973 dib0090_write_reg(state, 0x24, 0x02ed);
986 dib0090_write_reg(state, 0x01, state->dc->bb1);
987 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));
1045 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008);
1046 dib0090_write_reg(state, 0x1f, 0x7);
1060 dib0090_write_reg(state, 0x10, 0xdb09 | (1 << 10));
1061 dib0090_write_reg(state, 0x24, EN_UHF & 0x0fff);
1094 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */
1250 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));
1303 dib0090_write_reg(state, 0x15, (u16) FBDiv);
1305 dib0090_write_reg(state, 0x16, (Den << 8) | 1);
1307 dib0090_write_reg(state, 0x17, (u16) Rest);
1309 dib0090_write_reg(state, 0x19, lo5);
1311 dib0090_write_reg(state, 0x1c, lo6);
1317 dib0090_write_reg(state, 0x24, lo6 | EN_LO
1336 dib0090_write_reg(state, 0x10, 0x2B1);
1338 dib0090_write_reg(state, 0x1e, 0x0032);
1346 dib0090_write_reg(state, 0x18, lo4 | state->captrim);
1378 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
1386 dib0090_write_reg(state, 0x1e, 0x07ff);
1405 dib0090_write_reg(state, 0x10, (c << 13) | (i << 11) | (WBD
1410 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | (tune->lna_bias << 0));
1411 dib0090_write_reg(state, 0x0c, tune->v2i);
1412 dib0090_write_reg(state, 0x0d, tune->mix);
1413 dib0090_write_reg(state, 0x0e, tune->load);
1420 dib0090_write_reg(state, 0x0f, state->rf_lt_def);