Lines Matching refs:au8522_writereg
194 au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H, 0x00);
195 au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_L_REG018H, 0x00);
196 au8522_writereg(state, AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H, 0x00);
197 au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH, 0x00);
198 au8522_writereg(state, AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH, 0x00);
199 au8522_writereg(state, AU8522_TVDEC_VBI_USER_THRESH1_REG01CH, 0x00);
200 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH, 0x00);
201 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH, 0x00);
202 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H, 0x00);
203 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H,
205 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H,
207 au8522_writereg(state, AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H,
212 au8522_writereg(state, i, 0x40);
216 au8522_writereg(state, 0x44, 0x60);
220 au8522_writereg(state, AU8522_TVDEC_VBI_CTRL_H_REG017H,
231 au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
232 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
234 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
236 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
237 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
239 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
240 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
244 au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
248 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
251 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
254 au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
256 au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
258 au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
260 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
262 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
264 au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
266 au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
268 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
270 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
272 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
274 au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
276 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
278 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
280 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
282 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
284 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
286 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
288 au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
290 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
292 au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
293 au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
294 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
296 au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
297 au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
298 au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
300 au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
302 au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
304 au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
306 au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
308 au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
310 au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
312 au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
328 au8522_writereg(state, filter_coef[i].reg_name,
334 au8522_writereg(state, AU8522_REG42EH, 0x87);
335 au8522_writereg(state, AU8522_REG42FH, 0xa2);
336 au8522_writereg(state, AU8522_REG430H, 0xbf);
337 au8522_writereg(state, AU8522_REG431H, 0xcb);
338 au8522_writereg(state, AU8522_REG432H, 0xa1);
339 au8522_writereg(state, AU8522_REG433H, 0x41);
340 au8522_writereg(state, AU8522_REG434H, 0x88);
341 au8522_writereg(state, AU8522_REG435H, 0xc2);
342 au8522_writereg(state, AU8522_REG436H, 0x3c);
348 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
351 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
352 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
353 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
355 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H,
360 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
367 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
372 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
375 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
378 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
381 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H,
387 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
393 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
397 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H,
401 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
406 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
415 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
416 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
417 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
418 au8522_writereg(state, AU8522_I2C_CONTROL_REG1_REG091H, 0x80);
419 au8522_writereg(state, AU8522_I2C_CONTROL_REG0_REG090H, 0x84);
421 au8522_writereg(state, AU8522_ENA_USB_REG101H, 0x00);
422 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
423 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
424 au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
425 au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x40);
427 au8522_writereg(state, AU8522_GPIO_DATA_REG0E2H, 0x11);
429 au8522_writereg(state, AU8522_GPIO_DATA_REG0E2H, 0x00);
431 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
432 au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
433 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
435 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
461 au8522_writereg(state, lpfilter_coef[i].reg_name,
466 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
467 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
468 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
469 au8522_writereg(state, AU8522_I2C_CONTROL_REG1_REG091H, 0x80);
470 au8522_writereg(state, AU8522_I2C_CONTROL_REG0_REG090H, 0x84);
472 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x00);
474 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x9d);
476 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
477 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
478 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
480 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
481 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
482 au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
483 au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
485 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
486 au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
487 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
499 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
504 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
509 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
511 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
516 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
518 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
595 au8522_writereg(state, reg->reg, reg->val & 0xff);
605 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
608 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
613 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
650 au8522_writereg(state, 0xa4, 1 << 5);
665 au8522_writereg(state, 0x106, 1);
813 au8522_writereg(state, 0x106, 1);