Lines Matching defs:fe
299 static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
300 static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
301 static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
303 static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum,
306 static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
307 static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
309 static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
310 static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
313 static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
314 static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
315 static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
316 static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
318 static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
320 static u16 MXL_IFSynthInit(struct dvb_frontend *fe);
321 static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
323 static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
338 static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
340 struct mxl5005s_state *state = fe->tuner_priv;
357 mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
360 MXL_TuneRF(fe, RfFreqHz);
362 MXL_ControlRead(fe, IF_DIVVAL, &IfDivval);
364 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);
365 MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);
366 MXL_ControlWrite(fe, IF_DIVVAL, 8);
367 MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen);
375 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
381 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1);
382 MXL_ControlWrite(fe, IF_DIVVAL, IfDivval);
383 MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen);
391 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
403 static u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
405 struct mxl5005s_state *state = fe->tuner_priv;
723 static u16 MXL5005_ControlInit(struct dvb_frontend *fe)
725 struct mxl5005s_state *state = fe->tuner_priv;
1663 static void InitTunerControls(struct dvb_frontend *fe)
1665 MXL5005_RegisterInit(fe);
1666 MXL5005_ControlInit(fe);
1668 MXL5005_MXLControlInit(fe);
1672 static u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
1695 struct mxl5005s_state *state = fe->tuner_priv;
1714 InitTunerControls(fe);
1717 MXL_SynthIFLO_Calc(fe);
1722 static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
1724 struct mxl5005s_state *state = fe->tuner_priv;
1735 static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
1737 struct mxl5005s_state *state = fe->tuner_priv;
1756 static u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
1760 status += MXL_ControlWrite(fe, OVERRIDE_1, 1);
1761 status += MXL_ControlWrite(fe, OVERRIDE_2, 1);
1762 status += MXL_ControlWrite(fe, OVERRIDE_3, 1);
1763 status += MXL_ControlWrite(fe, OVERRIDE_4, 1);
1768 static u16 MXL_BlockInit(struct dvb_frontend *fe)
1770 struct mxl5005s_state *state = fe->tuner_priv;
1773 status += MXL_OverwriteICDefault(fe);
1776 status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0);
1779 status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1);
1780 status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2);
1781 status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0);
1782 status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1);
1783 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0);
1789 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0);
1792 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
1795 status += MXL_ControlWrite(fe,
1802 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1806 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1810 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT,
1817 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8);
1818 status += MXL_ControlWrite(fe,
1820 status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
1824 status += MXL_ControlWrite(fe, AGC_IF, 15);
1825 status += MXL_ControlWrite(fe, AGC_RF, 15);
1827 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
1830 status += MXL_ControlWrite(fe, AGC_IF, 0x0);
1833 status += MXL_ControlWrite(fe, AGC_IF, 0x1);
1836 status += MXL_ControlWrite(fe, AGC_IF, 0x2);
1839 status += MXL_ControlWrite(fe, AGC_IF, 0x3);
1842 status += MXL_ControlWrite(fe, AGC_IF, 0x4);
1845 status += MXL_ControlWrite(fe, AGC_IF, 0x5);
1848 status += MXL_ControlWrite(fe, AGC_IF, 0x6);
1851 status += MXL_ControlWrite(fe, AGC_IF, 0x7);
1854 status += MXL_ControlWrite(fe, AGC_IF, 0x9);
1857 status += MXL_ControlWrite(fe, AGC_IF, 0xA);
1860 status += MXL_ControlWrite(fe, AGC_IF, 0xB);
1863 status += MXL_ControlWrite(fe, AGC_IF, 0xC);
1866 status += MXL_ControlWrite(fe, AGC_IF, 0xD);
1869 status += MXL_ControlWrite(fe, AGC_IF, 0xE);
1872 status += MXL_ControlWrite(fe, AGC_IF, 0xF);
1875 status += MXL_IFSynthInit(fe);
1879 status += MXL_ControlWrite(fe, DRV_RES_SEL, 6);
1880 status += MXL_ControlWrite(fe, I_DRIVER, 2);
1883 status += MXL_ControlWrite(fe, DRV_RES_SEL, 4);
1884 status += MXL_ControlWrite(fe, I_DRIVER, 1);
1892 status += MXL_ControlWrite(fe, EN_AAF, 1);
1893 status += MXL_ControlWrite(fe, EN_3P, 1);
1894 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1895 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1899 status += MXL_ControlWrite(fe, EN_AAF, 1);
1900 status += MXL_ControlWrite(fe, EN_3P, 1);
1901 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1902 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
1905 status += MXL_ControlWrite(fe, EN_AAF, 0);
1906 status += MXL_ControlWrite(fe, EN_3P, 1);
1907 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1908 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
1912 status += MXL_ControlWrite(fe, EN_AAF, 1);
1913 status += MXL_ControlWrite(fe, EN_3P, 1);
1914 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
1915 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1918 status += MXL_ControlWrite(fe, EN_AAF, 0);
1919 status += MXL_ControlWrite(fe, EN_3P, 0);
1920 status += MXL_ControlWrite(fe, EN_AUX_3P, 0);
1921 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
1927 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1);
1929 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0);
1932 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1);
1934 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0);
1938 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1);
1940 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0);
1943 status += MXL_ControlWrite(fe, IF_SEL_DBL, 1);
1945 status += MXL_ControlWrite(fe, IF_SEL_DBL, 0);
1948 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3);
1950 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0);
1954 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0);
1956 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1);
1958 /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */
1961 status += MXL_ControlWrite(fe, TG_R_DIV,
1968 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
1969 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
1970 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
1971 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
1974 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
1975 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3);
1976 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
1979 status += MXL_ControlWrite(fe, RFA_FLR, 0);
1980 status += MXL_ControlWrite(fe, RFA_CEIL, 12);
1990 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
1991 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
1992 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
1993 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
1996 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
1997 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
1998 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2001 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2002 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2004 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2006 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2013 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2014 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2015 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2016 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2019 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
2020 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4);
2021 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2024 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2025 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2026 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1);
2028 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
2031 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2033 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2041 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2042 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2043 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2044 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2047 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2048 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2049 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2051 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2054 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2056 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2057 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2067 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2068 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2069 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2070 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2072 status += MXL_ControlWrite(fe, AGC_IF, 1);
2073 status += MXL_ControlWrite(fe, AGC_RF, 15);
2074 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2082 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2083 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2084 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2085 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2088 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2089 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2090 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2091 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2092 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
2097 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2098 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2099 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2100 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2106 static u16 MXL_IFSynthInit(struct dvb_frontend *fe)
2108 struct mxl5005s_state *state = fe->tuner_priv;
2123 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2124 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2128 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2129 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2133 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2134 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2138 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2139 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2143 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2144 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2148 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2149 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2153 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2154 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2158 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2159 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2166 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2167 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2171 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2172 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2176 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2177 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2181 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2182 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2186 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2187 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2191 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2192 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2196 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2197 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2201 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2202 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2206 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2207 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2211 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2212 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2216 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2217 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2221 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2222 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2226 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05);
2227 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2231 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10);
2232 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2236 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2237 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2241 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08);
2242 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2246 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2247 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2251 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2252 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2256 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04);
2257 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2261 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2262 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2266 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2267 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2271 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07);
2272 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C);
2276 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2277 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2281 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09);
2282 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2286 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06);
2287 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2291 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05);
2292 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08);
2299 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal);
2305 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal);
2318 static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
2320 struct mxl5005s_state *state = fe->tuner_priv;
2336 MXL_SynthRFTGLO_Calc(fe);
2356 status += MXL_ControlWrite(fe, DN_POLY, 2);
2357 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2358 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423);
2359 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2360 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
2363 status += MXL_ControlWrite(fe, DN_POLY, 3);
2364 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2365 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222);
2366 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2367 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
2370 status += MXL_ControlWrite(fe, DN_POLY, 3);
2371 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2372 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147);
2373 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2374 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
2377 status += MXL_ControlWrite(fe, DN_POLY, 3);
2378 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2379 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9);
2380 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2381 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
2384 status += MXL_ControlWrite(fe, DN_POLY, 3);
2385 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2386 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2387 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2388 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2391 status += MXL_ControlWrite(fe, DN_POLY, 3);
2392 status += MXL_ControlWrite(fe, DN_RFGAIN, 1);
2393 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2394 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0);
2395 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2398 status += MXL_ControlWrite(fe, DN_POLY, 3);
2399 status += MXL_ControlWrite(fe, DN_RFGAIN, 2);
2400 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0);
2401 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0);
2402 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3);
2410 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2411 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2414 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2415 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2418 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2419 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2422 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2423 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2426 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2427 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2430 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2431 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2434 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2435 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2438 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2439 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2442 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2443 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2446 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2447 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2450 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2451 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2454 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2455 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2458 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2459 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2462 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2463 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
2466 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
2467 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
2470 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
2471 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
2490 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2491 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2492 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2493 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2494 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2495 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2503 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2504 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2505 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2506 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2507 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2508 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2516 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2517 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2518 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2519 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2520 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2521 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2529 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2530 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2531 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2532 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2533 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2534 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
2542 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2543 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2544 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2545 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2546 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2547 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2);
2555 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2556 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2557 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2558 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2559 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2560 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2);
2568 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2569 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2570 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2571 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2572 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2573 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4);
2581 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2582 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2583 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2584 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2585 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2586 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2594 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2595 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2596 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2597 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2598 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2);
2599 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2607 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2608 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2609 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2610 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1);
2611 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2612 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2620 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
2621 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
2622 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2623 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1);
2624 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2625 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
2638 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3);
2642 MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4);
2649 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
2653 status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A);
2656 status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
2658 * status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1);
2660 * status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5);
2678 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6);
2679 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0);
2687 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1);
2688 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0);
2696 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC);
2697 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2705 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2706 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2714 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2715 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2);
2723 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2724 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3);
2732 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2733 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3);
2741 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8);
2742 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7);
2750 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0);
2751 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7);
2762 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval);
2765 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1);
2788 status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo);
2793 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN,
2796 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2798 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2804 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2805 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2806 status += MXL_SetGPIO(fe, 3, 1); /* Bank1 Off */
2807 status += MXL_SetGPIO(fe, 1, 1); /* Bank2 Off */
2808 status += MXL_SetGPIO(fe, 4, 1); /* Bank3 Off */
2812 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2813 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2816 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2817 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2818 status += MXL_SetGPIO(fe, 3, 0);
2819 status += MXL_SetGPIO(fe, 1, 1);
2820 status += MXL_SetGPIO(fe, 4, 1);
2823 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2824 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2825 status += MXL_SetGPIO(fe, 3, 1);
2826 status += MXL_SetGPIO(fe, 1, 0);
2827 status += MXL_SetGPIO(fe, 4, 1);
2830 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2831 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2832 status += MXL_SetGPIO(fe, 3, 1);
2833 status += MXL_SetGPIO(fe, 1, 0);
2834 status += MXL_SetGPIO(fe, 4, 0);
2837 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2838 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2839 status += MXL_SetGPIO(fe, 3, 1);
2840 status += MXL_SetGPIO(fe, 1, 1);
2841 status += MXL_SetGPIO(fe, 4, 0);
2844 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2845 status += MXL_ControlWrite(fe, DAC_DIN_B, 29);
2846 status += MXL_SetGPIO(fe, 3, 1);
2847 status += MXL_SetGPIO(fe, 1, 1);
2848 status += MXL_SetGPIO(fe, 4, 0);
2851 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2852 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2853 status += MXL_SetGPIO(fe, 3, 1);
2854 status += MXL_SetGPIO(fe, 1, 1);
2855 status += MXL_SetGPIO(fe, 4, 0);
2858 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2859 status += MXL_ControlWrite(fe, DAC_DIN_B, 16);
2860 status += MXL_SetGPIO(fe, 3, 1);
2861 status += MXL_SetGPIO(fe, 1, 1);
2862 status += MXL_SetGPIO(fe, 4, 1);
2865 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2866 status += MXL_ControlWrite(fe, DAC_DIN_B, 7);
2867 status += MXL_SetGPIO(fe, 3, 1);
2868 status += MXL_SetGPIO(fe, 1, 1);
2869 status += MXL_SetGPIO(fe, 4, 1);
2872 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2873 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2874 status += MXL_SetGPIO(fe, 3, 1);
2875 status += MXL_SetGPIO(fe, 1, 1);
2876 status += MXL_SetGPIO(fe, 4, 1);
2883 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2886 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2887 status += MXL_SetGPIO(fe, 4, 0);
2888 status += MXL_SetGPIO(fe, 3, 1);
2889 status += MXL_SetGPIO(fe, 1, 1);
2892 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2893 status += MXL_SetGPIO(fe, 4, 1);
2894 status += MXL_SetGPIO(fe, 3, 0);
2895 status += MXL_SetGPIO(fe, 1, 1);
2898 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2899 status += MXL_SetGPIO(fe, 4, 1);
2900 status += MXL_SetGPIO(fe, 3, 0);
2901 status += MXL_SetGPIO(fe, 1, 0);
2904 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
2905 status += MXL_SetGPIO(fe, 4, 1);
2906 status += MXL_SetGPIO(fe, 3, 1);
2907 status += MXL_SetGPIO(fe, 1, 0);
2910 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2911 status += MXL_SetGPIO(fe, 4, 1);
2912 status += MXL_SetGPIO(fe, 3, 1);
2913 status += MXL_SetGPIO(fe, 1, 0);
2916 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2917 status += MXL_SetGPIO(fe, 4, 1);
2918 status += MXL_SetGPIO(fe, 3, 1);
2919 status += MXL_SetGPIO(fe, 1, 0);
2922 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2923 status += MXL_SetGPIO(fe, 4, 1);
2924 status += MXL_SetGPIO(fe, 3, 1);
2925 status += MXL_SetGPIO(fe, 1, 1);
2928 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2929 status += MXL_SetGPIO(fe, 4, 1);
2930 status += MXL_SetGPIO(fe, 3, 1);
2931 status += MXL_SetGPIO(fe, 1, 1);
2934 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
2935 status += MXL_SetGPIO(fe, 4, 1);
2936 status += MXL_SetGPIO(fe, 3, 1);
2937 status += MXL_SetGPIO(fe, 1, 1);
2943 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
2946 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2947 status += MXL_SetGPIO(fe, 4, 0);
2948 status += MXL_SetGPIO(fe, 1, 1);
2949 status += MXL_SetGPIO(fe, 3, 1);
2952 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2953 status += MXL_SetGPIO(fe, 4, 0);
2954 status += MXL_SetGPIO(fe, 1, 0);
2955 status += MXL_SetGPIO(fe, 3, 1);
2958 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2959 status += MXL_SetGPIO(fe, 4, 1);
2960 status += MXL_SetGPIO(fe, 1, 0);
2961 status += MXL_SetGPIO(fe, 3, 1);
2964 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2965 status += MXL_SetGPIO(fe, 4, 1);
2966 status += MXL_SetGPIO(fe, 1, 0);
2967 status += MXL_SetGPIO(fe, 3, 0);
2970 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
2971 status += MXL_SetGPIO(fe, 4, 1);
2972 status += MXL_SetGPIO(fe, 1, 1);
2973 status += MXL_SetGPIO(fe, 3, 0);
2976 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2977 status += MXL_SetGPIO(fe, 4, 1);
2978 status += MXL_SetGPIO(fe, 1, 1);
2979 status += MXL_SetGPIO(fe, 3, 0);
2982 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
2983 status += MXL_SetGPIO(fe, 4, 1);
2984 status += MXL_SetGPIO(fe, 1, 1);
2985 status += MXL_SetGPIO(fe, 3, 1);
2992 status += MXL_ControlWrite(fe, DAC_DIN_A, 0);
2998 status += MXL_SetGPIO(fe, 3, 1);
2999 status += MXL_SetGPIO(fe, 1, 1);
3000 status += MXL_SetGPIO(fe, 4, 1);
3001 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3002 status += MXL_ControlWrite(fe, AGC_IF, 10);
3008 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3009 status += MXL_SetGPIO(fe, 4, 1);
3010 status += MXL_SetGPIO(fe, 1, 1);
3011 status += MXL_SetGPIO(fe, 3, 0);
3015 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3016 status += MXL_SetGPIO(fe, 4, 1);
3017 status += MXL_SetGPIO(fe, 1, 0);
3018 status += MXL_SetGPIO(fe, 3, 0);
3022 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3023 status += MXL_SetGPIO(fe, 4, 0);
3024 status += MXL_SetGPIO(fe, 1, 1);
3025 status += MXL_SetGPIO(fe, 3, 0);
3029 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3030 status += MXL_SetGPIO(fe, 4, 0);
3031 status += MXL_SetGPIO(fe, 1, 0);
3032 status += MXL_SetGPIO(fe, 3, 1);
3036 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3037 status += MXL_SetGPIO(fe, 4, 1);
3038 status += MXL_SetGPIO(fe, 1, 0);
3039 status += MXL_SetGPIO(fe, 3, 1);
3043 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3044 status += MXL_SetGPIO(fe, 4, 0);
3045 status += MXL_SetGPIO(fe, 1, 0);
3046 status += MXL_SetGPIO(fe, 3, 1);
3050 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0);
3051 status += MXL_SetGPIO(fe, 4, 0);
3052 status += MXL_SetGPIO(fe, 1, 1);
3053 status += MXL_SetGPIO(fe, 3, 1);
3057 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3058 status += MXL_SetGPIO(fe, 4, 0);
3059 status += MXL_SetGPIO(fe, 1, 1);
3060 status += MXL_SetGPIO(fe, 3, 1);
3064 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1);
3065 status += MXL_SetGPIO(fe, 4, 1);
3066 status += MXL_SetGPIO(fe, 1, 1);
3067 status += MXL_SetGPIO(fe, 3, 1);
3074 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3077 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3078 status += MXL_SetGPIO(fe, 4, 0);
3079 status += MXL_SetGPIO(fe, 1, 1);
3080 status += MXL_SetGPIO(fe, 3, 1);
3083 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3084 status += MXL_SetGPIO(fe, 4, 0);
3085 status += MXL_SetGPIO(fe, 1, 0);
3086 status += MXL_SetGPIO(fe, 3, 1);
3089 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3090 status += MXL_SetGPIO(fe, 4, 1);
3091 status += MXL_SetGPIO(fe, 1, 0);
3092 status += MXL_SetGPIO(fe, 3, 1);
3095 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3096 status += MXL_SetGPIO(fe, 4, 1);
3097 status += MXL_SetGPIO(fe, 1, 0);
3098 status += MXL_SetGPIO(fe, 3, 0);
3101 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3102 status += MXL_SetGPIO(fe, 4, 1);
3103 status += MXL_SetGPIO(fe, 1, 1);
3104 status += MXL_SetGPIO(fe, 3, 0);
3107 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3108 status += MXL_SetGPIO(fe, 4, 1);
3109 status += MXL_SetGPIO(fe, 1, 1);
3110 status += MXL_SetGPIO(fe, 3, 0);
3113 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3114 status += MXL_SetGPIO(fe, 4, 1);
3115 status += MXL_SetGPIO(fe, 1, 1);
3116 status += MXL_SetGPIO(fe, 3, 1);
3123 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3126 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3127 status += MXL_SetGPIO(fe, 4, 0);
3128 status += MXL_SetGPIO(fe, 1, 1);
3129 status += MXL_SetGPIO(fe, 3, 1);
3132 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3133 status += MXL_SetGPIO(fe, 4, 0);
3134 status += MXL_SetGPIO(fe, 1, 0);
3135 status += MXL_SetGPIO(fe, 3, 1);
3138 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3139 status += MXL_SetGPIO(fe, 4, 1);
3140 status += MXL_SetGPIO(fe, 1, 0);
3141 status += MXL_SetGPIO(fe, 3, 1);
3144 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3145 status += MXL_SetGPIO(fe, 4, 1);
3146 status += MXL_SetGPIO(fe, 1, 0);
3147 status += MXL_SetGPIO(fe, 3, 0);
3150 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3151 status += MXL_SetGPIO(fe, 4, 1);
3152 status += MXL_SetGPIO(fe, 1, 1);
3153 status += MXL_SetGPIO(fe, 3, 0);
3156 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3157 status += MXL_SetGPIO(fe, 4, 1);
3158 status += MXL_SetGPIO(fe, 1, 1);
3159 status += MXL_SetGPIO(fe, 3, 0);
3162 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3163 status += MXL_SetGPIO(fe, 4, 1);
3164 status += MXL_SetGPIO(fe, 1, 1);
3165 status += MXL_SetGPIO(fe, 3, 1);
3172 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3175 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3176 status += MXL_SetGPIO(fe, 4, 0);
3177 status += MXL_SetGPIO(fe, 1, 1);
3178 status += MXL_SetGPIO(fe, 3, 1);
3181 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3182 status += MXL_SetGPIO(fe, 4, 0);
3183 status += MXL_SetGPIO(fe, 1, 0);
3184 status += MXL_SetGPIO(fe, 3, 1);
3187 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3188 status += MXL_SetGPIO(fe, 4, 1);
3189 status += MXL_SetGPIO(fe, 1, 0);
3190 status += MXL_SetGPIO(fe, 3, 1);
3193 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3194 status += MXL_SetGPIO(fe, 4, 1);
3195 status += MXL_SetGPIO(fe, 1, 0);
3196 status += MXL_SetGPIO(fe, 3, 0);
3199 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3200 status += MXL_SetGPIO(fe, 4, 1);
3201 status += MXL_SetGPIO(fe, 1, 1);
3202 status += MXL_SetGPIO(fe, 3, 0);
3205 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3206 status += MXL_SetGPIO(fe, 4, 1);
3207 status += MXL_SetGPIO(fe, 1, 1);
3208 status += MXL_SetGPIO(fe, 3, 0);
3211 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3212 status += MXL_SetGPIO(fe, 4, 1);
3213 status += MXL_SetGPIO(fe, 1, 1);
3214 status += MXL_SetGPIO(fe, 3, 1);
3221 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3225 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3226 status += MXL_SetGPIO(fe, 4, 0);
3227 status += MXL_SetGPIO(fe, 1, 1);
3228 status += MXL_SetGPIO(fe, 3, 1);
3231 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3232 status += MXL_SetGPIO(fe, 4, 0);
3233 status += MXL_SetGPIO(fe, 1, 0);
3234 status += MXL_SetGPIO(fe, 3, 1);
3237 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3238 status += MXL_SetGPIO(fe, 4, 1);
3239 status += MXL_SetGPIO(fe, 1, 0);
3240 status += MXL_SetGPIO(fe, 3, 1);
3243 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3244 status += MXL_SetGPIO(fe, 4, 1);
3245 status += MXL_SetGPIO(fe, 1, 0);
3246 status += MXL_SetGPIO(fe, 3, 0);
3249 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3250 status += MXL_SetGPIO(fe, 4, 1);
3251 status += MXL_SetGPIO(fe, 1, 0);
3252 status += MXL_SetGPIO(fe, 3, 1);
3255 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3256 status += MXL_SetGPIO(fe, 4, 1);
3257 status += MXL_SetGPIO(fe, 1, 1);
3258 status += MXL_SetGPIO(fe, 3, 0);
3261 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3262 status += MXL_SetGPIO(fe, 4, 1);
3263 status += MXL_SetGPIO(fe, 1, 1);
3264 status += MXL_SetGPIO(fe, 3, 0);
3267 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3268 status += MXL_SetGPIO(fe, 4, 1);
3269 status += MXL_SetGPIO(fe, 1, 1);
3270 status += MXL_SetGPIO(fe, 3, 1);
3277 status += MXL_ControlWrite(fe, DAC_DIN_B, 0);
3284 status += MXL_SetGPIO(fe, 3, 1);
3285 status += MXL_SetGPIO(fe, 1, 1);
3286 status += MXL_SetGPIO(fe, 4, 1);
3287 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3290 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
3291 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
3292 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
3293 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
3296 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
3297 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
3298 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
3302 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
3307 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
3310 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5);
3315 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3316 status += MXL_SetGPIO(fe, 4, 0);
3317 status += MXL_SetGPIO(fe, 1, 1);
3318 status += MXL_SetGPIO(fe, 3, 1);
3321 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3322 status += MXL_SetGPIO(fe, 4, 0);
3323 status += MXL_SetGPIO(fe, 1, 0);
3324 status += MXL_SetGPIO(fe, 3, 1);
3327 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3328 status += MXL_SetGPIO(fe, 4, 1);
3329 status += MXL_SetGPIO(fe, 1, 0);
3330 status += MXL_SetGPIO(fe, 3, 1);
3333 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3334 status += MXL_SetGPIO(fe, 4, 1);
3335 status += MXL_SetGPIO(fe, 1, 0);
3336 status += MXL_SetGPIO(fe, 3, 0);
3339 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0);
3340 status += MXL_SetGPIO(fe, 4, 1);
3341 status += MXL_SetGPIO(fe, 1, 1);
3342 status += MXL_SetGPIO(fe, 3, 0);
3345 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3346 status += MXL_SetGPIO(fe, 4, 1);
3347 status += MXL_SetGPIO(fe, 1, 1);
3348 status += MXL_SetGPIO(fe, 3, 0);
3351 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1);
3352 status += MXL_SetGPIO(fe, 4, 1);
3353 status += MXL_SetGPIO(fe, 1, 1);
3354 status += MXL_SetGPIO(fe, 3, 1);
3361 static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
3366 status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1);
3372 status += MXL_ControlWrite(fe, GPIO_3, 0);
3373 status += MXL_ControlWrite(fe, GPIO_3B, 0);
3376 status += MXL_ControlWrite(fe, GPIO_3, 1);
3377 status += MXL_ControlWrite(fe, GPIO_3B, 1);
3380 status += MXL_ControlWrite(fe, GPIO_3, 0);
3381 status += MXL_ControlWrite(fe, GPIO_3B, 1);
3386 status += MXL_ControlWrite(fe, GPIO_4, 0);
3387 status += MXL_ControlWrite(fe, GPIO_4B, 0);
3390 status += MXL_ControlWrite(fe, GPIO_4, 1);
3391 status += MXL_ControlWrite(fe, GPIO_4B, 1);
3394 status += MXL_ControlWrite(fe, GPIO_4, 0);
3395 status += MXL_ControlWrite(fe, GPIO_4B, 1);
3402 static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
3408 status += MXL_ControlWrite_Group(fe, ControlNum, value, 1);
3410 status += MXL_ControlWrite_Group(fe, ControlNum, value, 2);
3413 status += MXL_ControlWrite_Group(fe, ControlNum, value, 3);
3418 static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum,
3421 struct mxl5005s_state *state = fe->tuner_priv;
3436 MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
3458 MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
3481 MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]),
3499 static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
3501 struct mxl5005s_state *state = fe->tuner_priv;
3514 static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
3516 struct mxl5005s_state *state = fe->tuner_priv;
3562 static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit,
3565 struct mxl5005s_state *state = fe->tuner_priv;
3593 static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum,
3606 status += MXL_BlockInit(fe);
3610 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3616 static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal,
3640 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3646 static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum,
3658 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
3679 static u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
3681 struct mxl5005s_state *state = fe->tuner_priv;
3685 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3686 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3687 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3688 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3689 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3690 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3691 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3694 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3695 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3696 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3697 status += MXL_ControlWrite(fe,
3702 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3703 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3704 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3705 status += MXL_ControlWrite(fe,
3709 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3710 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3711 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
3712 status += MXL_ControlWrite(fe,
3718 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3719 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3720 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3721 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3722 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3723 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3724 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3725 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3726 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3727 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
3730 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3731 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3732 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3733 status += MXL_ControlWrite(fe,
3738 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3739 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3740 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3741 status += MXL_ControlWrite(fe,
3745 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
3746 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3747 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
3748 status += MXL_ControlWrite(fe,
3754 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3755 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3756 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3757 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3758 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3759 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3760 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3761 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3762 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3763 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3766 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3767 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3768 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
3769 status += MXL_ControlWrite(fe,
3774 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3775 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3776 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
3777 status += MXL_ControlWrite(fe,
3781 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3782 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
3783 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
3784 status += MXL_ControlWrite(fe,
3790 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
3791 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
3792 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
3793 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
3794 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
3795 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
3796 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
3797 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3798 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3799 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3802 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3803 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3804 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3805 status += MXL_ControlWrite(fe,
3810 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3811 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3812 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3813 status += MXL_ControlWrite(fe,
3817 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
3818 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
3819 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
3820 status += MXL_ControlWrite(fe,
3828 static u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
3830 struct mxl5005s_state *state = fe->tuner_priv;
3834 status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1);
3847 static int mxl5005s_reset(struct dvb_frontend *fe)
3849 struct mxl5005s_state *state = fe->tuner_priv;
3858 if (fe->ops.i2c_gate_ctrl)
3859 fe->ops.i2c_gate_ctrl(fe, 1);
3866 if (fe->ops.i2c_gate_ctrl)
3867 fe->ops.i2c_gate_ctrl(fe, 0);
3875 static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch)
3877 struct mxl5005s_state *state = fe->tuner_priv;
3894 static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable,
3899 if (fe->ops.i2c_gate_ctrl)
3900 fe->ops.i2c_gate_ctrl(fe, 1);
3903 ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0);
3908 ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1);
3910 if (fe->ops.i2c_gate_ctrl)
3911 fe->ops.i2c_gate_ctrl(fe, 0);
3916 static int mxl5005s_init(struct dvb_frontend *fe)
3918 struct mxl5005s_state *state = fe->tuner_priv;
3922 return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ);
3925 static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type,
3928 struct mxl5005s_state *state = fe->tuner_priv;
3936 mxl5005s_reset(fe);
3943 mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
3945 mxl5005s_AssignTunerMode(fe, mod_type, bandwidth);
3948 MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
3950 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
3955 static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type,
3958 struct mxl5005s_state *state = fe->tuner_priv;
3961 InitTunerControls(fe);
3965 fe,
3984 static int mxl5005s_set_params(struct dvb_frontend *fe,
3987 struct mxl5005s_state *state = fe->tuner_priv;
3993 if (fe->ops.info.type == FE_ATSC) {
4031 ret = mxl5005s_reconfigure(fe, req_mode, req_bw);
4038 ret = mxl5005s_SetRfFreqHz(fe, params->frequency);
4044 static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency)
4046 struct mxl5005s_state *state = fe->tuner_priv;
4054 static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
4056 struct mxl5005s_state *state = fe->tuner_priv;
4064 static int mxl5005s_release(struct dvb_frontend *fe)
4067 kfree(fe->tuner_priv);
4068 fe->tuner_priv = NULL;
4088 struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
4099 state->frontend = fe;
4106 memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops,
4109 fe->tuner_priv = state;
4110 return fe;