Lines Matching refs:hw
68 return (readreg(cs->hw.mic.adr, cs->hw.mic.isac, offset));
74 writereg(cs->hw.mic.adr, cs->hw.mic.isac, offset, value);
80 readfifo(cs->hw.mic.adr, cs->hw.mic.isac, 0, data, size);
86 writefifo(cs->hw.mic.adr, cs->hw.mic.isac, 0, data, size);
92 return (readreg(cs->hw.mic.adr,
93 cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0)));
99 writereg(cs->hw.mic.adr,
100 cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0), value);
107 #define READHSCX(cs, nr, reg) readreg(cs->hw.mic.adr, \
108 cs->hw.mic.hscx, reg + (nr ? 0x40 : 0))
109 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.mic.adr, \
110 cs->hw.mic.hscx, reg + (nr ? 0x40 : 0), data)
112 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.mic.adr, \
113 cs->hw.mic.hscx, (nr ? 0x40 : 0), ptr, cnt)
115 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.mic.adr, \
116 cs->hw.mic.hscx, (nr ? 0x40 : 0), ptr, cnt)
128 val = readreg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_ISTA + 0x40);
132 val = readreg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_ISTA);
136 val = readreg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_ISTA + 0x40);
142 val = readreg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_ISTA);
148 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0xFF);
149 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0xFF);
150 writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0xFF);
151 writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0x0);
152 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0x0);
153 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0x0);
163 if (cs->hw.mic.cfg_reg)
164 release_region(cs->hw.mic.cfg_reg, bytecnt);
203 cs->hw.mic.cfg_reg = card->para[1];
205 cs->hw.mic.adr = cs->hw.mic.cfg_reg + MIC_ADR;
206 cs->hw.mic.isac = cs->hw.mic.cfg_reg + MIC_ISAC;
207 cs->hw.mic.hscx = cs->hw.mic.cfg_reg + MIC_HSCX;
209 if (!request_region(cs->hw.mic.cfg_reg, bytecnt, "mic isdn")) {
212 cs->hw.mic.cfg_reg,
213 cs->hw.mic.cfg_reg + bytecnt);
217 cs->hw.mic.cfg_reg, cs->irq);