Lines Matching refs:hw
151 struct _hfc4s8s_hw *hw; /* pointer to hardware area */
316 Read_hfc8_stable(hfc4s8s_hw * hw, int reg)
320 ref8 = Read_hfc8(hw, reg);
321 while (((in8 = Read_hfc8(hw, reg)) != ref8)) {
328 Read_hfc16_stable(hfc4s8s_hw * hw, int reg)
333 ref16 = Read_hfc16(hw, reg);
334 while (((in16 = Read_hfc16(hw, reg)) != ref16)) {
361 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
364 schedule_work(&l1->hw->tqueue);
377 Write_hfc8(l1->hw, R_ST_SEL,
379 Write_hfc8(l1->hw, A_ST_WR_STA,
394 Write_hfc8(l1->hw, R_ST_SEL,
396 Write_hfc8(l1->hw, A_ST_WR_STA,
441 l1->hw->mr.r_irq_fifo_blx[l1->st_num] |=
444 schedule_work(&l1->hw->tqueue);
460 l1->hw->mr.timer_usg_cnt++;
461 l1->hw->mr.
467 Write_hfc8(l1->hw, R_FIFO,
471 wait_busy(l1->hw);
472 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */
473 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */
474 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable TX interrupts for hdlc */
475 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
476 wait_busy(l1->hw);
478 Write_hfc8(l1->hw, R_FIFO,
482 wait_busy(l1->hw);
483 Write_hfc8(l1->hw, A_CON_HDLC, 0xc); /* HDLC mode, flag fill, connect ST */
484 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */
485 Write_hfc8(l1->hw, A_IRQ_MSK, 1); /* enable RX interrupts for hdlc */
486 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
488 Write_hfc8(l1->hw, R_ST_SEL,
490 l1->hw->mr.r_ctrl0 |=
492 Write_hfc8(l1->hw, A_ST_CTRL0,
493 l1->hw->mr.r_ctrl0);
507 l1->hw->mr.
513 l1->hw->mr.timer_usg_cnt++;
514 Write_hfc8(l1->hw, R_FIFO,
518 wait_busy(l1->hw);
519 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */
520 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */
521 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */
522 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
523 wait_busy(l1->hw);
525 Write_hfc8(l1->hw, R_FIFO,
529 wait_busy(l1->hw);
530 Write_hfc8(l1->hw, A_CON_HDLC, 0xf); /* Transparent mode, 1 fill, connect ST */
531 Write_hfc8(l1->hw, A_SUBCH_CFG, 0); /* 8 bits */
532 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */
533 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
535 Write_hfc8(l1->hw, R_ST_SEL,
537 l1->hw->mr.r_ctrl0 |=
539 Write_hfc8(l1->hw, A_ST_CTRL0,
540 l1->hw->mr.r_ctrl0);
556 l1->hw->mr.
562 l1->hw->mr.
568 l1->hw->mr.timer_usg_cnt--;
569 Write_hfc8(l1->hw, R_FIFO,
573 wait_busy(l1->hw);
574 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable TX interrupts */
575 wait_busy(l1->hw);
576 Write_hfc8(l1->hw, R_FIFO,
580 wait_busy(l1->hw);
581 Write_hfc8(l1->hw, A_IRQ_MSK, 0); /* disable RX interrupts */
582 Write_hfc8(l1->hw, R_ST_SEL,
584 l1->hw->mr.r_ctrl0 &=
586 Write_hfc8(l1->hw, A_ST_CTRL0,
587 l1->hw->mr.r_ctrl0);
612 if (l1->hw->mr.timer_usg_cnt) {
613 Write_hfc8(l1->hw, R_IRQMSK_MISC,
616 Write_hfc8(l1->hw, R_IRQMSK_MISC, 0);
646 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
647 Write_hfc8(l1->hw, A_ST_WR_STA, 0x11);
653 Write_hfc8(l1->hw, A_ST_WR_STA, 0x1);
657 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
658 Write_hfc8(l1->hw, A_ST_WR_STA, 0x13);
663 Write_hfc8(l1->hw, R_ST_SEL, l1->st_num);
664 Write_hfc8(l1->hw, A_ST_WR_STA, 0x3);
685 Write_hfc8(l1p->hw, R_FIFO,
687 wait_busy(l1p->hw);
689 f1 = Read_hfc8_stable(l1p->hw, A_F1);
690 f2 = Read_hfc8(l1p->hw, A_F2);
700 z1 = Read_hfc16_stable(l1p->hw, A_Z1);
701 z2 = Read_hfc16(l1p->hw, A_Z2);
711 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2);
712 wait_busy(l1p->hw);
722 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 2);
723 wait_busy(l1p->hw);
729 SetRegAddr(l1p->hw, A_FIFO_DATA0);
734 Read_hfc32(l1p->hw, A_FIFO_DATA0);
736 fRead_hfc32(l1p->hw);
743 Read_hfc8(l1p->hw, A_FIFO_DATA0);
745 fRead_hfc8(l1p->hw);
748 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1);
749 wait_busy(l1p->hw);
757 SetRegAddr(l1p->hw, A_FIFO_DATA0);
763 Read_hfc32(l1p->hw, A_FIFO_DATA0);
765 *((unsigned long *) cp) = fRead_hfc32(l1p->hw);
773 *cp++ = Read_hfc8(l1p->hw, A_FIFO_DATA0);
775 *cp++ = fRead_hfc8(l1p->hw);
778 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */
779 wait_busy(l1p->hw);
813 Write_hfc8(l1->hw, R_FIFO,
815 wait_busy(l1->hw);
818 f1 = Read_hfc8_stable(l1->hw, A_F1);
819 f2 = Read_hfc8(l1->hw, A_F2);
823 z1 = Read_hfc16_stable(l1->hw, A_Z1);
824 z2 = Read_hfc16(l1->hw, A_Z2);
858 Write_hfc8(l1->hw, A_INC_RES_FIFO, 2); /* reset fifo */
859 wait_busy(l1->hw);
863 SetRegAddr(l1->hw, A_FIFO_DATA0);
869 Read_hfc32(l1->hw, A_FIFO_DATA0);
872 fRead_hfc32(l1->hw);
880 *(bch->rx_ptr++) = Read_hfc8(l1->hw, A_FIFO_DATA0);
882 *(bch->rx_ptr++) = fRead_hfc8(l1->hw);
887 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1);
888 wait_busy(l1->hw);
924 Write_hfc8(l1p->hw, R_FIFO, (l1p->st_num * 8 + 4));
925 wait_busy(l1p->hw);
927 f1 = Read_hfc8(l1p->hw, A_F1);
928 f2 = Read_hfc8_stable(l1p->hw, A_F2);
944 SetRegAddr(l1p->hw, A_FIFO_DATA0);
949 fWrite_hfc32(l1p->hw, A_FIFO_DATA0,
952 SetRegAddr(l1p->hw, A_FIFO_DATA0);
953 fWrite_hfc32(l1p->hw, *(unsigned long *) cp);
961 fWrite_hfc8(l1p->hw, A_FIFO_DATA0, *cp++);
964 fWrite_hfc8(l1p->hw, *cp++);
968 Write_hfc8(l1p->hw, A_INC_RES_FIFO, 1); /* increment f counter */
969 wait_busy(l1p->hw);
991 Write_hfc8(l1->hw, R_FIFO,
993 wait_busy(l1->hw);
997 hdlc_num = Read_hfc8(l1->hw, A_F1) & MAX_F_CNT;
999 (Read_hfc8_stable(l1->hw, A_F2) & MAX_F_CNT);
1009 l1->hw->mr.fifo_slow_timer_service[l1->
1019 l1->hw->mr.fifo_slow_timer_service[l1->st_num] |=
1022 l1->hw->mr.fifo_slow_timer_service[l1->st_num] &=
1025 max = Read_hfc16_stable(l1->hw, A_Z2);
1026 max -= Read_hfc16(l1->hw, A_Z1);
1041 SetRegAddr(l1->hw, A_FIFO_DATA0);
1045 fWrite_hfc32(l1->hw, A_FIFO_DATA0,
1048 fWrite_hfc32(l1->hw, *(unsigned long *) cp);
1056 fWrite_hfc8(l1->hw, A_FIFO_DATA0, *cp++);
1058 fWrite_hfc8(l1->hw, *cp++);
1064 Write_hfc8(l1->hw, A_INC_RES_FIFO, 1);
1072 Write_hfc8(l1->hw, R_FIFO,
1075 wait_busy(l1->hw);
1089 hfc4s8s_hw *hw = container_of(work, hfc4s8s_hw, tqueue);
1097 l1p = hw->l1;
1099 if ((b & hw->mr.r_irq_statech)) {
1101 hw->mr.r_irq_statech &= ~b;
1106 Write_hfc8(l1p->hw, R_ST_SEL,
1109 Read_hfc8(l1p->hw,
1135 Write_hfc8(hw, A_ST_WR_STA,
1148 Write_hfc8(l1p->hw, R_ST_SEL,
1151 Read_hfc8(l1p->hw,
1192 l1p->hw->cardnum,
1204 fifo_stat = hw->mr.r_irq_fifo_blx;
1205 l1p = hw->l1;
1206 while (idx < hw->driver_data.max_st_ports) {
1208 if (hw->mr.timer_irq) {
1209 *fifo_stat |= hw->mr.fifo_rx_trans_enables[idx];
1210 if (hw->fifo_sched_cnt <= 0) {
1212 hw->mr.fifo_slow_timer_service[l1p->
1264 if (hw->fifo_sched_cnt <= 0)
1265 hw->fifo_sched_cnt += (1 << (7 - TRANS_TIMER_MODE));
1266 hw->mr.timer_irq = 0; /* clear requested timer irq */
1275 hfc4s8s_hw *hw = dev_id;
1281 if (!hw || !(hw->mr.r_irq_ctrl & M_GLOB_IRQ_EN))
1286 old_ioreg = GetRegAddr(hw);
1290 hw->mr.r_irq_statech |=
1291 (Read_hfc8(hw, R_SCI) & hw->mr.r_irqmsk_statchg);
1293 (b = (Read_hfc8(hw, R_STATUS) & (M_MISC_IRQSTA | M_FR_IRQSTA)))
1294 && !hw->mr.r_irq_statech) {
1296 SetRegAddr(hw, old_ioreg);
1302 if (Read_hfc8(hw, R_IRQ_MISC) & M_TI_IRQ) {
1303 hw->mr.timer_irq = 1;
1304 hw->fifo_sched_cnt--;
1308 if ((ovr = Read_hfc8(hw, R_IRQ_OVIEW))) {
1309 hw->mr.r_irq_oview |= ovr;
1311 ovp = hw->mr.r_irq_fifo_blx;
1314 *ovp |= Read_hfc8(hw, idx);
1323 schedule_work(&hw->tqueue);
1326 SetRegAddr(hw, old_ioreg);
1335 chipreset(hfc4s8s_hw * hw)
1339 spin_lock_irqsave(&hw->lock, flags);
1340 Write_hfc8(hw, R_CTRL, 0); /* use internal RAM */
1341 Write_hfc8(hw, R_RAM_MISC, 0); /* 32k*8 RAM */
1342 Write_hfc8(hw, R_FIFO_MD, 0); /* fifo mode 386 byte/fifo simple mode */
1343 Write_hfc8(hw, R_CIRM, M_SRES); /* reset chip */
1344 hw->mr.r_irq_ctrl = 0; /* interrupt is inactive */
1345 spin_unlock_irqrestore(&hw->lock, flags);
1348 Write_hfc8(hw, R_CIRM, 0); /* disable reset */
1349 wait_busy(hw);
1351 Write_hfc8(hw, R_PCM_MD0, M_PCM_MD); /* master mode */
1352 Write_hfc8(hw, R_RAM_MISC, M_FZ_MD); /* transmit fifo option */
1353 if (hw->driver_data.clock_mode == 1)
1354 Write_hfc8(hw, R_BRG_PCM_CFG, M_PCM_CLK); /* PCM clk / 2 */
1355 Write_hfc8(hw, R_TI_WD, TRANS_TIMER_MODE); /* timer interval */
1357 memset(&hw->mr, 0, sizeof(hw->mr));
1364 hfc_hardware_enable(hfc4s8s_hw * hw, int enable, int nt_mode)
1372 hw->nt_mode = nt_mode;
1375 hw->mr.r_irq_ctrl = M_FIFO_IRQ;
1376 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1377 hw->mr.r_irqmsk_statchg = 0;
1378 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg);
1379 Write_hfc8(hw, R_PWM_MD, 0x80);
1380 Write_hfc8(hw, R_PWM1, 26);
1382 Write_hfc8(hw, R_ST_SYNC, M_AUTO_SYNC);
1385 for (i = 0; i < hw->driver_data.max_st_ports; i++) {
1386 hw->mr.r_irqmsk_statchg |= (1 << i);
1387 Write_hfc8(hw, R_SCI_MSK, hw->mr.r_irqmsk_statchg);
1388 Write_hfc8(hw, R_ST_SEL, i);
1389 Write_hfc8(hw, A_ST_CLK_DLY,
1391 hw->mr.r_ctrl0 = ((nt_mode) ? CTRL0_NT : CTRL0_TE);
1392 Write_hfc8(hw, A_ST_CTRL0, hw->mr.r_ctrl0);
1393 Write_hfc8(hw, A_ST_CTRL2, 3);
1394 Write_hfc8(hw, A_ST_WR_STA, 0); /* enable state machine */
1396 hw->l1[i].enabled = 1;
1397 hw->l1[i].nt_mode = nt_mode;
1401 Write_hfc8(hw, R_FIFO, i * 8 + 7); /* E fifo */
1402 wait_busy(hw);
1403 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */
1404 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1405 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */
1406 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */
1407 wait_busy(hw);
1410 Write_hfc8(hw, R_FIFO, i * 8 + 5); /* RX fifo */
1411 wait_busy(hw);
1412 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */
1413 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1414 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */
1415 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */
1416 wait_busy(hw);
1419 Write_hfc8(hw, R_FIFO, i * 8 + 4); /* TX fifo */
1420 wait_busy(hw);
1421 Write_hfc8(hw, A_CON_HDLC, 0x11); /* HDLC mode, 1 fill, connect ST */
1422 Write_hfc8(hw, A_SUBCH_CFG, 2); /* only 2 bits */
1423 Write_hfc8(hw, A_IRQ_MSK, 1); /* enable interrupt */
1424 Write_hfc8(hw, A_INC_RES_FIFO, 2); /* reset fifo */
1425 wait_busy(hw);
1428 sprintf(if_name, "hfc4s8s_%d%d_", hw->cardnum, i);
1431 (&hw->l1[i].d_if, hw->l1[i].b_table, if_name,
1434 hw->l1[i].enabled = 0;
1435 hw->mr.r_irqmsk_statchg &= ~(1 << i);
1436 Write_hfc8(hw, R_SCI_MSK,
1437 hw->mr.r_irqmsk_statchg);
1444 spin_lock_irqsave(&hw->lock, flags);
1445 hw->mr.r_irq_ctrl |= M_GLOB_IRQ_EN;
1446 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1447 spin_unlock_irqrestore(&hw->lock, flags);
1450 spin_lock_irqsave(&hw->lock, flags);
1451 hw->mr.r_irq_ctrl &= ~M_GLOB_IRQ_EN;
1452 Write_hfc8(hw, R_IRQ_CTRL, hw->mr.r_irq_ctrl);
1453 spin_unlock_irqrestore(&hw->lock, flags);
1455 for (i = hw->driver_data.max_st_ports - 1; i >= 0; i--) {
1456 hw->l1[i].enabled = 0;
1457 hisax_unregister(&hw->l1[i].d_if);
1458 del_timer(&hw->l1[i].l1_timer);
1459 skb_queue_purge(&hw->l1[i].d_tx_queue);
1460 skb_queue_purge(&hw->l1[i].b_ch[0].tx_queue);
1461 skb_queue_purge(&hw->l1[i].b_ch[1].tx_queue);
1463 chipreset(hw);
1471 release_pci_ports(hfc4s8s_hw * hw)
1473 pci_write_config_word(hw->pdev, PCI_COMMAND, 0);
1475 if (hw->membase)
1476 iounmap((void *) hw->membase);
1478 if (hw->iobase)
1479 release_region(hw->iobase, 8);
1487 enable_pci_ports(hfc4s8s_hw * hw)
1490 pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
1492 pci_write_config_word(hw->pdev, PCI_COMMAND, PCI_ENA_REGIO);
1501 setup_instance(hfc4s8s_hw * hw)
1509 l1p = hw->l1 + i;
1511 l1p->hw = hw;
1517 l1p->d_if.ifc.priv = hw->l1 + i;
1523 l1p->b_ch[0].l1p = hw->l1 + i;
1531 l1p->b_ch[1].l1p = hw->l1 + i;
1537 enable_pci_ports(hw);
1538 chipreset(hw);
1540 i = Read_hfc8(hw, R_CHIP_ID) >> CHIP_ID_SHIFT;
1541 if (i != hw->driver_data.chip_id) {
1544 i, hw->driver_data.chip_id);
1548 i = Read_hfc8(hw, R_CHIP_RV) & 0xf;
1555 INIT_WORK(&hw->tqueue, hfc4s8s_bh);
1558 (hw->irq, hfc4s8s_interrupt, IRQF_SHARED, hw->card_name, hw)) {
1561 hw->irq);
1567 hw->hw_membase, hw->irq);
1571 hw->iobase, hw->irq);
1574 hfc_hardware_enable(hw, 1, 0);
1579 hw->irq = 0;
1580 release_pci_ports(hw);
1581 kfree(hw);
1593 hfc4s8s_hw *hw;
1595 if (!(hw = kzalloc(sizeof(hfc4s8s_hw), GFP_ATOMIC))) {
1600 hw->pdev = pdev;
1606 hw->cardnum = card_cnt;
1607 sprintf(hw->card_name, "hfc4s8s_%d", hw->cardnum);
1609 driver_data->device_name, hw->card_name, pci_name(pdev));
1611 spin_lock_init(&hw->lock);
1613 hw->driver_data = *driver_data;
1614 hw->irq = pdev->irq;
1615 hw->iobase = pci_resource_start(pdev, 0);
1618 hw->hw_membase = (u_char *) pci_resource_start(pdev, 1);
1619 hw->membase = ioremap((ulong) hw->hw_membase, 256);
1621 if (!request_region(hw->iobase, 8, hw->card_name)) {
1624 hw->iobase);
1629 pci_set_drvdata(pdev, hw);
1630 err = setup_instance(hw);
1636 kfree(hw);
1646 hfc4s8s_hw *hw = pci_get_drvdata(pdev);
1648 printk(KERN_INFO "HFC-4S/8S: removing card %d\n", hw->cardnum);
1649 hfc_hardware_enable(hw, 0, 0);
1651 if (hw->irq)
1652 free_irq(hw->irq, hw);
1653 hw->irq = 0;
1654 release_pci_ports(hw);
1658 kfree(hw);