Lines Matching refs:hw
83 outb(idx, cs->hw.avm.cfg_reg + 4);
84 val = inb(cs->hw.avm.isac + (offset & 0xf));
93 outb(idx, cs->hw.avm.cfg_reg + 4);
94 outb(value, cs->hw.avm.isac + (offset & 0xf));
100 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
101 insb(cs->hw.avm.isac, data, size);
107 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4);
108 outsb(cs->hw.avm.isac, data, size);
117 outl(idx, cs->hw.avm.cfg_reg + 4);
118 val = inl(cs->hw.avm.isac + offset);
127 outl(idx, cs->hw.avm.cfg_reg + 4);
128 outl(value, cs->hw.avm.isac + offset);
137 outb(idx, cs->hw.avm.cfg_reg + 4);
138 val = inb(cs->hw.avm.isac + offset);
147 outb(idx, cs->hw.avm.cfg_reg + 4);
148 outb(value, cs->hw.avm.isac + offset);
179 'A' + bcs->channel, which, bcs->hw.hdlc.ctrl.ctrl);
181 WriteHDLCPCI(bcs->cs, bcs->channel, HDLC_STATUS, bcs->hw.hdlc.ctrl.ctrl);
185 bcs->hw.hdlc.ctrl.sr.mode);
188 bcs->hw.hdlc.ctrl.sr.xml);
191 bcs->hw.hdlc.ctrl.sr.cmd);
204 bcs->hw.hdlc.ctrl.ctrl = 0;
213 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
214 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
222 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
223 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_TRANS;
225 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
227 bcs->hw.hdlc.ctrl.sr.cmd = 0;
233 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS;
234 bcs->hw.hdlc.ctrl.sr.mode = HDLC_MODE_ITF_FLG;
236 bcs->hw.hdlc.ctrl.sr.cmd = HDLC_CMD_XRS;
238 bcs->hw.hdlc.ctrl.sr.cmd = 0;
255 if (bcs->hw.hdlc.rcvidx + count > HSCX_BUFMAX) {
260 p = bcs->hw.hdlc.rcvbuf + bcs->hw.hdlc.rcvidx;
262 bcs->hw.hdlc.rcvidx += count;
264 outl(idx, cs->hw.avm.cfg_reg + 4);
267 *ptr++ = in_be32((unsigned *)(cs->hw.avm.isac +_IO_BASE));
269 *ptr++ = inl(cs->hw.avm.isac);
274 outb(idx, cs->hw.avm.cfg_reg + 4);
276 *p++ = inb(cs->hw.avm.isac);
308 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XME;
314 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XME;
322 bcs->hw.hdlc.count += count;
323 bcs->hw.hdlc.ctrl.sr.xml = ((count == fifo_size) ? 0 : count);
328 out_be32((unsigned *)(cs->hw.avm.isac +_IO_BASE), *ptr++);
330 outl(*ptr++, cs->hw.avm.isac);
336 outb(*p++, cs->hw.avm.isac);
365 bcs->hw.hdlc.ctrl.sr.xml = 0;
366 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_RRS;
368 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_RRS;
370 bcs->hw.hdlc.rcvidx = 0;
378 if (!(skb = dev_alloc_skb(bcs->hw.hdlc.rcvidx)))
381 memcpy(skb_put(skb, bcs->hw.hdlc.rcvidx),
382 bcs->hw.hdlc.rcvbuf, bcs->hw.hdlc.rcvidx);
385 bcs->hw.hdlc.rcvidx = 0;
392 bcs->hw.hdlc.rcvidx = 0;
402 skb_push(bcs->tx_skb, bcs->hw.hdlc.count);
403 bcs->tx_cnt += bcs->hw.hdlc.count;
404 bcs->hw.hdlc.count = 0;
409 bcs->hw.hdlc.ctrl.sr.xml = 0;
410 bcs->hw.hdlc.ctrl.sr.cmd |= HDLC_CMD_XRS;
412 bcs->hw.hdlc.ctrl.sr.cmd &= ~HDLC_CMD_XRS;
425 bcs->ackcnt += bcs->hw.hdlc.count;
430 bcs->hw.hdlc.count = 0;
435 bcs->hw.hdlc.count = 0;
496 bcs->hw.hdlc.count = 0;
508 bcs->hw.hdlc.count = 0;
546 kfree(bcs->hw.hdlc.rcvbuf);
547 bcs->hw.hdlc.rcvbuf = NULL;
564 if (!(bcs->hw.hdlc.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
573 kfree(bcs->hw.hdlc.rcvbuf);
574 bcs->hw.hdlc.rcvbuf = NULL;
583 bcs->hw.hdlc.rcvidx = 0;
623 sval = inb(cs->hw.avm.cfg_reg + 2);
646 outb(AVM_STATUS0_RESET | AVM_STATUS0_DIS_TIMER, cs->hw.avm.cfg_reg + 2);
648 outb(AVM_STATUS0_DIS_TIMER | AVM_STATUS0_RES_TIMER | AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2);
649 outb(AVM_STATUS1_ENA_IOM | cs->irq, cs->hw.avm.cfg_reg + 3);
651 printk(KERN_INFO "AVM PCI/PnP: S1 %x\n", inb(cs->hw.avm.cfg_reg + 3));
666 outb(0, cs->hw.avm.cfg_reg + 2);
667 release_region(cs->hw.avm.cfg_reg, 32);
676 cs->hw.avm.cfg_reg + 2);
679 AVM_STATUS0_ENA_IRQ, cs->hw.avm.cfg_reg + 2);
694 cs->hw.avm.isac = cs->hw.avm.cfg_reg + 0x10;
695 if (!request_region(cs->hw.avm.cfg_reg, 32,
699 cs->hw.avm.cfg_reg,
700 cs->hw.avm.cfg_reg + 31);
705 val = inl(cs->hw.avm.cfg_reg);
713 val = inb(cs->hw.avm.cfg_reg);
714 ver = inb(cs->hw.avm.cfg_reg + 1);
725 cs->irq, cs->hw.avm.cfg_reg);
773 cs->hw.avm.cfg_reg =
780 if (!cs->hw.avm.cfg_reg) {
820 cs->hw.avm.cfg_reg = pci_resource_start(dev_avm, 1);
821 if (!cs->hw.avm.cfg_reg) {
854 cs->hw.avm.cfg_reg = card->para[1];