Lines Matching defs:isar
32 #include "isar.h"
50 waitforHIA(struct isar_hw *isar, int timeout)
53 u8 val = isar->read_reg(isar->hw, ISAR_HIA);
58 val = isar->read_reg(isar->hw, ISAR_HIA);
60 pr_debug("%s: HIA after %dus\n", isar->name, timeout - t);
66 * if msg is NULL use isar->buf
69 send_mbox(struct isar_hw *isar, u8 his, u8 creg, u8 len, u8 *msg)
71 if (!waitforHIA(isar, 1000))
74 isar->write_reg(isar->hw, ISAR_CTRL_H, creg);
75 isar->write_reg(isar->hw, ISAR_CTRL_L, len);
76 isar->write_reg(isar->hw, ISAR_WADR, 0);
78 msg = isar->buf;
80 isar->write_fifo(isar->hw, ISAR_MBOX, msg, len);
81 if (isar->ch[0].bch.debug & DEBUG_HW_BFIFO) {
86 isar->log, 256, 1);
87 pr_debug("%s: %s %02x: %s\n", isar->name,
88 __func__, l, isar->log);
93 isar->write_reg(isar->hw, ISAR_HIS, his);
94 waitforHIA(isar, 1000);
100 * if msg is NULL use isar->buf
103 rcv_mbox(struct isar_hw *isar, u8 *msg)
106 msg = isar->buf;
107 isar->write_reg(isar->hw, ISAR_RADR, 0);
108 if (msg && isar->clsb) {
109 isar->read_fifo(isar->hw, ISAR_MBOX, msg, isar->clsb);
110 if (isar->ch[0].bch.debug & DEBUG_HW_BFIFO) {
113 while (l < (int)isar->clsb) {
114 hex_dump_to_buffer(msg + l, isar->clsb - l, 32,
115 1, isar->log, 256, 1);
116 pr_debug("%s: %s %02x: %s\n", isar->name,
117 __func__, l, isar->log);
122 isar->write_reg(isar->hw, ISAR_IIA, 0);
126 get_irq_infos(struct isar_hw *isar)
128 isar->iis = isar->read_reg(isar->hw, ISAR_IIS);
129 isar->cmsb = isar->read_reg(isar->hw, ISAR_CTRL_H);
130 isar->clsb = isar->read_reg(isar->hw, ISAR_CTRL_L);
131 pr_debug("%s: rcv_mbox(%02x,%02x,%d)\n", isar->name,
132 isar->iis, isar->cmsb, isar->clsb);
141 poll_mbox(struct isar_hw *isar, int maxdelay)
146 irq = isar->read_reg(isar->hw, ISAR_IRQBIT);
152 get_irq_infos(isar);
153 rcv_mbox(isar, NULL);
156 isar->name, isar->clsb, maxdelay - t);
161 ISARVersion(struct isar_hw *isar)
166 isar->write_reg(isar->hw, ISAR_IRQBIT, 0);
167 isar->buf[0] = ISAR_MSG_HWVER;
168 isar->buf[1] = 0;
169 isar->buf[2] = 1;
170 if (!send_mbox(isar, ISAR_HIS_VNR, 0, 3, NULL))
172 if (!poll_mbox(isar, 1000))
174 if (isar->iis == ISAR_IIS_VNR) {
175 if (isar->clsb == 1) {
176 ver = isar->buf[0] & 0xf;
185 load_firmware(struct isar_hw *isar, const u8 *buf, int size)
187 u32 saved_debug = isar->ch[0].bch.debug;
200 if (1 != isar->version) {
202 isar->name, isar->version);
206 isar->ch[0].bch.debug &= ~DEBUG_HW_BFIFO;
208 isar->name, size/2, size);
212 spin_lock_irqsave(isar->hwlock, flags);
213 isar->write_reg(isar->hw, ISAR_IRQBIT, 0);
214 spin_unlock_irqrestore(isar->hwlock, flags);
225 isar->name, size, cnt + left);
229 spin_lock_irqsave(isar->hwlock, flags);
230 if (!send_mbox(isar, ISAR_HIS_DKEY, blk_head.d_key & 0xff,
236 if (!poll_mbox(isar, 1000)) {
241 spin_unlock_irqrestore(isar->hwlock, flags);
242 if ((isar->iis != ISAR_IIS_DKEY) || isar->cmsb || isar->clsb) {
244 isar->iis, isar->cmsb, isar->clsb);
254 mp = isar->buf;
261 pr_debug("%s: load %3d words at %04x\n", isar->name,
270 spin_lock_irqsave(isar->hwlock, flags);
271 if (!send_mbox(isar, ISAR_HIS_FIRM, 0, nom, NULL)) {
276 if (!poll_mbox(isar, 1000)) {
281 spin_unlock_irqrestore(isar->hwlock, flags);
282 if ((isar->iis != ISAR_IIS_FIRM) ||
283 isar->cmsb || isar->clsb) {
285 isar->iis, isar->cmsb, isar->clsb);
291 isar->name, blk_head.len);
293 isar->ch[0].bch.debug = saved_debug;
298 isar->buf[0] = 0xff;
299 isar->buf[1] = 0xfe;
300 isar->bstat = 0;
301 spin_lock_irqsave(isar->hwlock, flags);
302 if (!send_mbox(isar, ISAR_HIS_STDSP, 0, 2, NULL)) {
307 if (!poll_mbox(isar, 1000)) {
312 if ((isar->iis != ISAR_IIS_STDSP) || isar->cmsb || isar->clsb) {
314 isar->iis, isar->cmsb, isar->clsb);
318 pr_debug("%s: ISAR start dsp success\n", isar->name);
322 isar->write_reg(isar->hw, ISAR_IRQBIT, ISAR_IRQSTA);
323 spin_unlock_irqrestore(isar->hwlock, flags);
325 while ((!isar->bstat) && cnt) {
335 isar->name, isar->bstat);
340 isar->iis = 0;
341 spin_lock_irqsave(isar->hwlock, flags);
342 if (!send_mbox(isar, ISAR_HIS_DIAG, ISAR_CTRL_STST, 0, NULL)) {
347 spin_unlock_irqrestore(isar->hwlock, flags);
349 while ((isar->iis != ISAR_IIS_DIAG) && cnt) {
359 if ((isar->cmsb == ISAR_CTRL_STST) && (isar->clsb == 1)
360 && (isar->buf[0] == 0))
361 pr_debug("%s: ISAR selftest OK\n", isar->name);
364 isar->cmsb, isar->clsb, isar->buf[0]);
368 spin_lock_irqsave(isar->hwlock, flags);
369 isar->iis = 0;
370 if (!send_mbox(isar, ISAR_HIS_DIAG, ISAR_CTRL_SWVER, 0, NULL)) {
375 spin_unlock_irqrestore(isar->hwlock, flags);
377 while ((isar->iis != ISAR_IIS_DIAG) && cnt) {
387 if ((isar->cmsb == ISAR_CTRL_SWVER) && (isar->clsb == 1)) {
389 isar->name, isar->buf[0]);
392 " cnt(%d)\n", isar->name, isar->cmsb,
393 isar->clsb, cnt);
398 spin_lock_irqsave(isar->hwlock, flags);
399 isar_setup(isar);
400 spin_unlock_irqrestore(isar->hwlock, flags);
403 spin_lock_irqsave(isar->hwlock, flags);
405 isar->ch[0].bch.debug = saved_debug;
408 isar->write_reg(isar->hw, ISAR_IRQBIT, 0);
409 spin_unlock_irqrestore(isar->hwlock, flags);
671 sel_bch_isar(struct isar_hw *isar, u8 dpath)
673 struct isar_ch *base = &isar->ch[0];
731 check_send(struct isar_hw *isar, u8 rdm)
735 pr_debug("%s: rdm %x\n", isar->name, rdm);
737 ch = sel_bch_isar(isar, 1);
747 ch = sel_bch_isar(isar, 2);
1047 mISDNisar_irq(struct isar_hw *isar)
1051 get_irq_infos(isar);
1052 switch (isar->iis & ISAR_IIS_MSCMSD) {
1054 ch = sel_bch_isar(isar, isar->iis >> 6);
1059 isar->name, isar->iis, isar->cmsb,
1060 isar->clsb);
1061 isar->write_reg(isar->hw, ISAR_IIA, 0);
1065 isar->write_reg(isar->hw, ISAR_IIA, 0);
1066 isar->bstat |= isar->cmsb;
1067 check_send(isar, isar->cmsb);
1071 ch = sel_bch_isar(isar, isar->iis >> 6);
1073 if (isar->cmsb == BSTEV_TBO)
1075 if (isar->cmsb == BSTEV_RBO)
1080 isar->name, isar->iis>>6, isar->cmsb);
1081 isar->write_reg(isar->hw, ISAR_IIA, 0);
1084 ch = sel_bch_isar(isar, isar->iis >> 6);
1086 rcv_mbox(isar, NULL);
1088 isar_pump_statev_modem(ch, isar->cmsb);
1090 isar_pump_statev_fax(ch, isar->cmsb);
1093 tt = isar->cmsb | 0x30;
1106 isar->name, ch->bch.state,
1107 isar->cmsb);
1110 isar->name, isar->iis, isar->cmsb,
1111 isar->clsb);
1112 isar->write_reg(isar->hw, ISAR_IIA, 0);
1116 ch = sel_bch_isar(isar, isar->iis >> 6);
1118 rcv_mbox(isar, NULL);
1122 isar->name, isar->iis, isar->cmsb,
1123 isar->clsb);
1124 isar->write_reg(isar->hw, ISAR_IIA, 0);
1130 rcv_mbox(isar, NULL);
1133 rcv_mbox(isar, NULL);
1134 pr_debug("%s: invalid msg his:%x\n", isar->name, isar->cmsb);
1137 rcv_mbox(isar, NULL);
1139 isar->name, isar->iis, isar->cmsb, isar->clsb);
1456 isar_setup(struct isar_hw *isar)
1465 send_mbox(isar, (i ? ISAR_HIS_DPS2 : ISAR_HIS_DPS1) |
1467 isar->ch[i].mml = msg;
1468 isar->ch[i].bch.state = 0;
1469 isar->ch[i].dpath = i + 1;
1470 modeisar(&isar->ch[i], ISDN_P_NONE);
1549 pr_debug("%s: isar: new mod\n", ich->is->name);
1630 free_isar(struct isar_hw *isar)
1632 modeisar(&isar->ch[0], ISDN_P_NONE);
1633 modeisar(&isar->ch[1], ISDN_P_NONE);
1634 del_timer(&isar->ch[0].ftimer);
1635 del_timer(&isar->ch[1].ftimer);
1636 test_and_clear_bit(FLG_INITIALIZED, &isar->ch[0].bch.Flags);
1637 test_and_clear_bit(FLG_INITIALIZED, &isar->ch[1].bch.Flags);
1641 init_isar(struct isar_hw *isar)
1646 isar->version = ISARVersion(isar);
1647 if (isar->ch[0].bch.debug & DEBUG_HW)
1649 isar->name, isar->version, 3 - cnt);
1650 if (isar->version == 1)
1652 isar->ctrl(isar->hw, HW_RESET_REQ, 0);
1654 if (isar->version != 1)
1656 isar->ch[0].ftimer.function = &ftimer_handler;
1657 isar->ch[0].ftimer.data = (long)&isar->ch[0];
1658 init_timer(&isar->ch[0].ftimer);
1659 test_and_set_bit(FLG_INITIALIZED, &isar->ch[0].bch.Flags);
1660 isar->ch[1].ftimer.function = &ftimer_handler;
1661 isar->ch[1].ftimer.data = (long)&isar->ch[1];
1662 init_timer(&isar->ch[1].ftimer);
1663 test_and_set_bit(FLG_INITIALIZED, &isar->ch[1].bch.Flags);
1668 isar_open(struct isar_hw *isar, struct channel_req *rq)
1676 bch = &isar->ch[rq->adr.channel - 1].bch;
1686 mISDNisar_init(struct isar_hw *isar, void *hw)
1690 isar->hw = hw;
1692 isar->ch[i].bch.nr = i + 1;
1693 mISDN_initbchannel(&isar->ch[i].bch, MAX_DATA_MEM);
1694 isar->ch[i].bch.ch.nr = i + 1;
1695 isar->ch[i].bch.ch.send = &isar_l2l1;
1696 isar->ch[i].bch.ch.ctrl = isar_bctrl;
1697 isar->ch[i].bch.hw = hw;
1698 isar->ch[i].is = isar;
1701 isar->init = &init_isar;
1702 isar->release = &free_isar;
1703 isar->firmware = &load_firmware;
1704 isar->open = &isar_open;