Lines Matching refs:hw
281 struct inf_hw *hw = dev_id;
284 spin_lock(&hw->lock);
285 val = inb((u32)hw->cfg.start + DIVA_PCI_CTRL);
287 spin_unlock(&hw->lock);
290 hw->irqcnt++;
291 mISDNipac_irq(&hw->ipac, irqloops);
292 spin_unlock(&hw->lock);
299 struct inf_hw *hw = dev_id;
302 spin_lock(&hw->lock);
303 val = readb(hw->cfg.p);
305 spin_unlock(&hw->lock);
308 hw->irqcnt++;
309 mISDNipac_irq(&hw->ipac, irqloops);
310 writeb(PITA_INT0_STATUS, hw->cfg.p); /* ACK PITA INT0 */
311 spin_unlock(&hw->lock);
318 struct inf_hw *hw = dev_id;
321 spin_lock(&hw->lock);
322 val = inb((u32)hw->cfg.start + TIGER_AUX_STATUS);
324 spin_unlock(&hw->lock);
327 hw->irqcnt++;
328 mISDNipac_irq(&hw->ipac, irqloops);
329 spin_unlock(&hw->lock);
336 struct inf_hw *hw = dev_id;
339 spin_lock(&hw->lock);
340 val = inb((u32)hw->cfg.start + ELSA_IRQ_ADDR);
342 spin_unlock(&hw->lock);
345 hw->irqcnt++;
346 mISDNipac_irq(&hw->ipac, irqloops);
347 spin_unlock(&hw->lock);
354 struct inf_hw *hw = dev_id;
357 spin_lock(&hw->lock);
358 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
360 spin_unlock(&hw->lock);
363 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
364 hw->irqcnt++;
365 mISDNipac_irq(&hw->ipac, irqloops);
366 spin_unlock(&hw->lock);
373 struct inf_hw *hw = dev_id;
376 spin_lock(&hw->lock);
377 ret = mISDNipac_irq(&hw->ipac, irqloops);
378 spin_unlock(&hw->lock);
385 struct inf_hw *hw = dev_id;
388 spin_lock(&hw->lock);
389 val = hw->ipac.read_reg(hw, IPAC_ISTA);
391 spin_unlock(&hw->lock);
394 hw->irqcnt++;
395 mISDNipac_irq(&hw->ipac, irqloops);
396 spin_unlock(&hw->lock);
401 enable_hwirq(struct inf_hw *hw)
406 switch (hw->ci->typ) {
409 writel(PITA_INT0_ENABLE, hw->cfg.p);
413 outb(TIGER_IRQ_BIT, (u32)hw->cfg.start + TIGER_AUX_IRQMASK);
416 outb(QS1000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
419 outb(QS3000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
422 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
424 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
427 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
429 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
433 (u32)hw->cfg.start + GAZEL_INCSR);
437 (u32)hw->cfg.start + GAZEL_INCSR);
445 disable_hwirq(struct inf_hw *hw)
450 switch (hw->ci->typ) {
453 writel(0, hw->cfg.p);
457 outb(0, (u32)hw->cfg.start + TIGER_AUX_IRQMASK);
460 outb(QS1000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
463 outb(QS3000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR);
466 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
468 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
471 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
473 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR);
477 outb(0, (u32)hw->cfg.start + GAZEL_INCSR);
485 ipac_chip_reset(struct inf_hw *hw)
487 hw->ipac.write_reg(hw, IPAC_POTA2, 0x20);
489 hw->ipac.write_reg(hw, IPAC_POTA2, 0x00);
491 hw->ipac.write_reg(hw, IPAC_CONF, hw->ipac.conf);
492 hw->ipac.write_reg(hw, IPAC_MASK, 0xc0);
496 reset_inf(struct inf_hw *hw)
502 pr_notice("%s: resetting card\n", hw->name);
503 switch (hw->ci->typ) {
506 outb(0, (u32)hw->cfg.start + DIVA_PCI_CTRL);
508 outb(DIVA_RESET_BIT, (u32)hw->cfg.start + DIVA_PCI_CTRL);
510 outb(9, (u32)hw->cfg.start + 0x69);
512 (u32)hw->cfg.start + DIVA_PCI_CTRL);
516 hw->cfg.p + PITA_MISC_REG);
518 writel(PITA_PARA_MPX_MODE, hw->cfg.p + PITA_MISC_REG);
523 hw->cfg.p + PITA_MISC_REG);
526 hw->cfg.p + PITA_MISC_REG);
531 ipac_chip_reset(hw);
532 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff);
533 hw->ipac.write_reg(hw, IPAC_AOE, 0x00);
534 hw->ipac.write_reg(hw, IPAC_PCFG, 0x12);
538 ipac_chip_reset(hw);
539 hw->ipac.write_reg(hw, IPAC_ACFG, 0x00);
540 hw->ipac.write_reg(hw, IPAC_AOE, 0x3c);
541 hw->ipac.write_reg(hw, IPAC_ATX, 0xff);
546 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
548 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
550 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
552 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR);
556 val = inl((u32)hw->cfg.start + GAZEL_CNTRL);
558 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
561 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
563 hw->ipac.isac.adf2 = 0x87;
564 hw->ipac.hscx[0].slot = 0x1f;
565 hw->ipac.hscx[0].slot = 0x23;
568 val = inl((u32)hw->cfg.start + GAZEL_CNTRL);
570 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
573 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
575 ipac_chip_reset(hw);
576 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff);
577 hw->ipac.write_reg(hw, IPAC_AOE, 0x00);
578 hw->ipac.conf = 0x01; /* IOM off */
583 enable_hwirq(hw);
587 inf_ctrl(struct inf_hw *hw, u32 cmd, u_long arg)
593 reset_inf(hw);
597 hw->name, __func__, cmd, arg);
605 init_irq(struct inf_hw *hw)
610 if (!hw->ci->irqfunc)
612 ret = request_irq(hw->irq, hw->ci->irqfunc, IRQF_SHARED, hw->name, hw);
614 pr_info("%s: couldn't get interrupt %d\n", hw->name, hw->irq);
618 spin_lock_irqsave(&hw->lock, flags);
619 reset_inf(hw);
620 ret = hw->ipac.init(&hw->ipac);
622 spin_unlock_irqrestore(&hw->lock, flags);
624 hw->name, ret);
627 spin_unlock_irqrestore(&hw->lock, flags);
630 pr_notice("%s: IRQ %d count %d\n", hw->name,
631 hw->irq, hw->irqcnt);
632 if (!hw->irqcnt) {
634 hw->name, hw->irq, 3 - cnt);
638 free_irq(hw->irq, hw);
643 release_io(struct inf_hw *hw)
645 if (hw->cfg.mode) {
646 if (hw->cfg.p) {
647 release_mem_region(hw->cfg.start, hw->cfg.size);
648 iounmap(hw->cfg.p);
650 release_region(hw->cfg.start, hw->cfg.size);
651 hw->cfg.mode = AM_NONE;
653 if (hw->addr.mode) {
654 if (hw->addr.p) {
655 release_mem_region(hw->addr.start, hw->addr.size);
656 iounmap(hw->addr.p);
658 release_region(hw->addr.start, hw->addr.size);
659 hw->addr.mode = AM_NONE;
664 setup_io(struct inf_hw *hw)
668 if (hw->ci->cfg_mode) {
669 hw->cfg.start = pci_resource_start(hw->pdev, hw->ci->cfg_bar);
670 hw->cfg.size = pci_resource_len(hw->pdev, hw->ci->cfg_bar);
671 if (hw->ci->cfg_mode == AM_MEMIO) {
672 if (!request_mem_region(hw->cfg.start, hw->cfg.size,
673 hw->name))
676 if (!request_region(hw->cfg.start, hw->cfg.size,
677 hw->name))
682 "already in use\n", hw->name,
683 (ulong)hw->cfg.start, (ulong)hw->cfg.size);
686 if (hw->ci->cfg_mode == AM_MEMIO)
687 hw->cfg.p = ioremap(hw->cfg.start, hw->cfg.size);
688 hw->cfg.mode = hw->ci->cfg_mode;
691 hw->name, (ulong)hw->cfg.start,
692 (ulong)hw->cfg.size, hw->ci->cfg_mode);
695 if (hw->ci->addr_mode) {
696 hw->addr.start = pci_resource_start(hw->pdev, hw->ci->addr_bar);
697 hw->addr.size = pci_resource_len(hw->pdev, hw->ci->addr_bar);
698 if (hw->ci->addr_mode == AM_MEMIO) {
699 if (!request_mem_region(hw->addr.start, hw->addr.size,
700 hw->name))
703 if (!request_region(hw->addr.start, hw->addr.size,
704 hw->name))
709 "already in use\n", hw->name,
710 (ulong)hw->addr.start, (ulong)hw->addr.size);
713 if (hw->ci->addr_mode == AM_MEMIO)
714 hw->addr.p = ioremap(hw->addr.start, hw->addr.size);
715 hw->addr.mode = hw->ci->addr_mode;
718 hw->name, (ulong)hw->addr.start,
719 (ulong)hw->addr.size, hw->ci->addr_mode);
723 switch (hw->ci->typ) {
726 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX;
727 hw->isac.mode = hw->cfg.mode;
728 hw->isac.a.io.ale = (u32)hw->cfg.start + DIVA_ISAC_ALE;
729 hw->isac.a.io.port = (u32)hw->cfg.start + DIVA_ISAC_PORT;
730 hw->hscx.mode = hw->cfg.mode;
731 hw->hscx.a.io.ale = (u32)hw->cfg.start + DIVA_HSCX_ALE;
732 hw->hscx.a.io.port = (u32)hw->cfg.start + DIVA_HSCX_PORT;
735 hw->ipac.type = IPAC_TYPE_IPAC;
736 hw->ipac.isac.off = 0x80;
737 hw->isac.mode = hw->addr.mode;
738 hw->isac.a.p = hw->addr.p;
739 hw->hscx.mode = hw->addr.mode;
740 hw->hscx.a.p = hw->addr.p;
743 hw->ipac.type = IPAC_TYPE_IPACX;
744 hw->isac.mode = hw->addr.mode;
745 hw->isac.a.p = hw->addr.p;
746 hw->hscx.mode = hw->addr.mode;
747 hw->hscx.a.p = hw->addr.p;
751 hw->ipac.type = IPAC_TYPE_IPAC;
752 hw->ipac.isac.off = 0x80;
753 hw->isac.mode = hw->cfg.mode;
754 hw->isac.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE;
755 hw->isac.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT;
756 hw->hscx.mode = hw->cfg.mode;
757 hw->hscx.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE;
758 hw->hscx.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT;
759 outb(0xff, (ulong)hw->cfg.start);
761 outb(0x00, (ulong)hw->cfg.start);
763 outb(TIGER_IOMASK, (ulong)hw->cfg.start + TIGER_AUX_CTRL);
767 hw->ipac.type = IPAC_TYPE_IPAC;
768 hw->ipac.isac.off = 0x80;
769 hw->isac.a.io.ale = (u32)hw->addr.start;
770 hw->isac.a.io.port = (u32)hw->addr.start + 1;
771 hw->isac.mode = hw->addr.mode;
772 hw->hscx.a.io.ale = (u32)hw->addr.start;
773 hw->hscx.a.io.port = (u32)hw->addr.start + 1;
774 hw->hscx.mode = hw->addr.mode;
777 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX;
778 hw->isac.mode = hw->addr.mode;
779 hw->isac.a.io.ale = (u32)hw->addr.start + NICCY_ISAC_ALE;
780 hw->isac.a.io.port = (u32)hw->addr.start + NICCY_ISAC_PORT;
781 hw->hscx.mode = hw->addr.mode;
782 hw->hscx.a.io.ale = (u32)hw->addr.start + NICCY_HSCX_ALE;
783 hw->hscx.a.io.port = (u32)hw->addr.start + NICCY_HSCX_PORT;
786 hw->ipac.type = IPAC_TYPE_IPAC;
787 hw->ipac.isac.off = 0x80;
788 hw->isac.a.io.ale = (u32)hw->addr.start;
789 hw->isac.a.io.port = hw->isac.a.io.ale + 4;
790 hw->isac.mode = hw->addr.mode;
791 hw->hscx.a.io.ale = hw->isac.a.io.ale;
792 hw->hscx.a.io.port = hw->isac.a.io.port;
793 hw->hscx.mode = hw->addr.mode;
796 hw->ipac.type = IPAC_TYPE_IPAC;
797 hw->ipac.isac.off = 0x80;
798 hw->isac.a.io.ale = (u32)hw->addr.start + 0x08;
799 hw->isac.a.io.port = hw->isac.a.io.ale + 4;
800 hw->isac.mode = hw->addr.mode;
801 hw->hscx.a.io.ale = hw->isac.a.io.ale;
802 hw->hscx.a.io.port = hw->isac.a.io.port;
803 hw->hscx.mode = hw->addr.mode;
806 hw->ipac.type = IPAC_TYPE_IPAC;
807 hw->ipac.isac.off = 0x80;
808 hw->isac.a.io.ale = (u32)hw->addr.start + 0x10;
809 hw->isac.a.io.port = hw->isac.a.io.ale + 4;
810 hw->isac.mode = hw->addr.mode;
811 hw->hscx.a.io.ale = hw->isac.a.io.ale;
812 hw->hscx.a.io.port = hw->isac.a.io.port;
813 hw->hscx.mode = hw->addr.mode;
816 hw->ipac.type = IPAC_TYPE_IPAC;
817 hw->ipac.isac.off = 0x80;
818 hw->isac.a.io.ale = (u32)hw->addr.start + 0x20;
819 hw->isac.a.io.port = hw->isac.a.io.ale + 4;
820 hw->isac.mode = hw->addr.mode;
821 hw->hscx.a.io.ale = hw->isac.a.io.ale;
822 hw->hscx.a.io.port = hw->isac.a.io.port;
823 hw->hscx.mode = hw->addr.mode;
826 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX;
827 hw->ipac.isac.off = 0x80;
828 hw->isac.mode = hw->addr.mode;
829 hw->isac.a.io.port = (u32)hw->addr.start;
830 hw->hscx.mode = hw->addr.mode;
831 hw->hscx.a.io.port = hw->isac.a.io.port;
834 hw->ipac.type = IPAC_TYPE_IPAC;
835 hw->ipac.isac.off = 0x80;
836 hw->isac.mode = hw->addr.mode;
837 hw->isac.a.io.ale = (u32)hw->addr.start;
838 hw->isac.a.io.port = (u32)hw->addr.start + GAZEL_IPAC_DATA_PORT;
839 hw->hscx.mode = hw->addr.mode;
840 hw->hscx.a.io.ale = hw->isac.a.io.ale;
841 hw->hscx.a.io.port = hw->isac.a.io.port;
846 switch (hw->isac.mode) {
848 ASSIGN_FUNC_IPAC(MIO, hw->ipac);
851 ASSIGN_FUNC_IPAC(IND, hw->ipac);
854 ASSIGN_FUNC_IPAC(IO, hw->ipac);