Lines Matching refs:cspec
788 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
790 return readq(&dd->cspec->cregbase[regno]);
797 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
799 return readl(&dd->cspec->cregbase[regno]);
1416 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1551 errs &= dd->cspec->errormask;
1552 msg = dd->cspec->emsgbuf;
1557 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1582 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask,
1701 ppd->dd->cspec->r1 ?
1873 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
1876 if (dd->cspec->num_msix_entries) {
1928 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1972 hwerrs &= dd->cspec->hwerrmask;
1986 dd->cspec->stay_in_freeze) {
2005 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2006 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2052 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2058 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2075 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2077 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2078 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2321 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2324 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2352 if (ppd->dd->cspec->r1)
2463 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2464 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2478 dd->cspec->extctrl = extctl;
2479 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2480 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2496 dd->cspec->main_int_mask = ~0ULL;
2497 n = dd->cspec->num_msix_entries;
2501 dd->cspec->num_msix_entries = 0;
2503 free_irq(dd->cspec->msix_entries[i].vector,
2504 dd->cspec->msix_arg[i]);
2515 if (dd->cspec->irq) {
2516 free_irq(dd->cspec->irq, dd);
2517 dd->cspec->irq = 0;
2527 kfree(dd->cspec->cntrs);
2528 kfree(dd->cspec->sendchkenable);
2529 kfree(dd->cspec->sendgrhchk);
2530 kfree(dd->cspec->sendibchk);
2531 kfree(dd->cspec->msix_entries);
2532 kfree(dd->cspec->msix_arg);
2540 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2541 dd->cspec->gpio_mask &= ~mask;
2542 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2543 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2602 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2642 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2663 dd->cspec->gpio_mask &= ~gpio_irq;
2664 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2693 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
2706 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
2749 istat &= dd->cspec->main_int_mask;
3029 if (!dd->cspec->num_msix_entries) {
3045 dd->cspec->irq = dd->pcidev->irq;
3046 dd->cspec->main_int_mask = ~0ULL;
3054 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3084 ret = request_irq(dd->cspec->msix_entries[msixnum].vector,
3093 dd->cspec->msix_entries[msixnum].vector,
3098 dd->cspec->msix_arg[msixnum] = arg;
3113 dd->cspec->main_int_mask = mask;
3212 msix_entries = dd->cspec->num_msix_entries;
3220 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3293 dd->cspec->msix_entries[i].entry = i;
3311 &dd->cspec->num_msix_entries,
3312 dd->cspec->msix_entries))
3450 if (rcd->dd->cspec->r1)
3476 dd->cspec->numctxts = nchipctxts;
3514 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3529 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3532 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3533 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt,
3877 if (ppd->dd->cspec->r1) {
4056 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4158 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4570 dd->cspec->ncntrs = i;
4573 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
4575 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
4576 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
4578 if (!dd->cspec->cntrs)
4583 dd->cspec->nportcntrs = i - 1;
4584 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
4586 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
4600 ret = dd->cspec->cntrnamelen;
4606 u64 *cntr = dd->cspec->cntrs;
4609 ret = dd->cspec->ncntrs * sizeof(u64);
4616 for (i = 0; i < dd->cspec->ncntrs; i++)
4635 ret = dd->cspec->portcntrnamelen;
4645 ret = dd->cspec->nportcntrs * sizeof(u64);
4652 for (i = 0; i < dd->cspec->nportcntrs; i++) {
4723 ppd->dd->cspec->r1 ?
4737 if (!dd->cspec->num_msix_entries)
4767 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
4779 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
5223 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5275 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5276 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5277 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5278 new_out = (dd->cspec->gpio_out & ~mask) | out;
5280 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5282 dd->cspec->gpio_out = new_out;
5283 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5364 * The chip base addresses in cspec and cpspec have to be set
5373 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5535 !ppd->dd->cspec->r1 && QSFP_IS_CU(qd->cache.tech)) ?
5555 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5556 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
5557 dd->cspec->gpio_mask |= mod_prs_bit;
5558 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5559 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
5560 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5789 if (ppd->dd->cspec->r1)
5819 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
5821 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
5857 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
5895 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
5897 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
5902 spin_lock_init(&dd->cspec->rcvmod_lock);
5903 spin_lock_init(&dd->cspec->gpio_lock);
5918 dd->cspec->r1 = dd->minrev == 1;
5927 dd->cspec->sendchkenable = kmalloc(sbufcnt *
5928 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
5929 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
5930 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
5931 dd->cspec->sendibchk = kmalloc(sbufcnt *
5932 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
5933 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
5934 !dd->cspec->sendibchk) {
5967 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
5969 dd->cspec->hwerrmask = ~0ULL;
5972 dd->cspec->hwerrmask &=
5989 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
5993 dd->cspec->int_enable_mask &= ~(
6004 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6008 dd->cspec->int_enable_mask &= ~(
6066 if (ppd->dd->cspec->r1)
6176 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6179 dd->cspec->sdmabufcnt = 0;
6182 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6183 dd->cspec->sdmabufcnt;
6184 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6185 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6197 dd->cspec->updthresh_dflt = updthresh;
6198 dd->cspec->updthresh = updthresh;
6229 last = dd->cspec->lastbuf_for_pio;
6316 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6318 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6321 dd->cspec->sdmabufcnt);
6447 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
6508 clear_bit(i, dd->cspec->sendchkenable);
6520 set_bit(i, dd->cspec->sendchkenable);
6526 set_bit(i, dd->cspec->sendibchk);
6527 clear_bit(i, dd->cspec->sendgrhchk);
6532 dd->cspec->updthresh != dd->cspec->updthresh_dflt
6536 < dd->cspec->updthresh_dflt)
6541 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
6543 dd->sendctrl |= (dd->cspec->updthresh &
6554 clear_bit(i, dd->cspec->sendibchk);
6555 set_bit(i, dd->cspec->sendgrhchk);
6559 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
6560 dd->cspec->updthresh = (rcd->piocnt /
6563 dd->sendctrl |= (dd->cspec->updthresh &
6578 dd->cspec->sendchkenable[i]);
6582 dd->cspec->sendgrhchk[i]);
6584 dd->cspec->sendibchk[i]);
6714 dd->cspec->msix_entries = kmalloc(tabsize *
6716 dd->cspec->msix_arg = kmalloc(tabsize *
6718 if (!dd->cspec->msix_entries || !dd->cspec->msix_arg) {
6723 dd->cspec->msix_entries[i].entry = i;
6725 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries))
6729 dd->cspec->num_msix_entries = tabsize;
7286 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7296 ppd->dd->cspec->r1 ?
7306 if (!ppd->dd->cspec->r1) {
7406 if (!ppd->dd->cspec->r1)
7605 if (!ppd->dd->cspec->r1)
7608 dd->cspec->recovery_ports_initted++;
7611 if (!both && dd->cspec->recovery_ports_initted == 1) {
7639 if (dd->cspec->recovery_ports_initted != 1)
7652 ppd->dd->cspec->stay_in_freeze = 1;