Lines Matching refs:SYM_MASK
144 #define SYM_MASK(regname, fldname) ((u64) \
156 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
157 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
158 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
159 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
160 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
162 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
181 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
182 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
183 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
184 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
336 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
338 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
831 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
832 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
1036 SYM_MASK(EXTStatus, MemBISTDisabled)
1038 SYM_MASK(EXTStatus, MemBISTEndTest)
1052 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1053 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1054 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1055 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1056 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1057 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1058 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1064 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1068 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1070 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1071 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1078 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1079 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1080 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1081 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1082 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1086 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1088 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1110 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1112 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1139 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted"},
1182 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1219 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), .msg = #fldname }
1365 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1367 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1370 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1372 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1375 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1377 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1380 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1381 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1382 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1384 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1385 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1386 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1392 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1403 SYM_MASK(SendCtrl_0, SDmaCleanup));
1409 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1677 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1681 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1818 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1825 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1832 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1834 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1836 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1981 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
2119 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2172 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2175 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2184 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2213 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2269 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2299 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2317 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2322 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2367 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2382 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2581 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2583 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
3573 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
3601 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
3722 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
3736 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
3756 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3759 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3773 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
3902 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
3908 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
3958 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
3963 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
4059 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4061 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4063 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4065 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4067 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4069 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4082 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4200 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4202 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4204 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4209 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4211 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4222 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4226 SYM_MASK(SendCtrl, Disarm) | i);
4239 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4240 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4241 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4249 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4253 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4254 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4761 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
4762 SYM_MASK(IBPCSConfig_0, xcv_treset) |
4763 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
4770 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
4778 SYM_MASK(HwErrClear, statusValidNoEopClear));
5120 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5123 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5130 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5144 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5145 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5154 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5398 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5399 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5400 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5401 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5402 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5403 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5404 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5767 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
5780 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
5790 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
5820 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
5973 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
5974 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
5989 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
5991 | SYM_MASK(HwErrMask,
5994 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
5995 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
5996 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
5997 SYM_MASK(IntMask, SDmaIntMask_0) |
5998 SYM_MASK(IntMask, ErrIntMask_0) |
5999 SYM_MASK(IntMask, SendDoneIntMask_0));
6004 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6006 | SYM_MASK(HwErrMask,
6009 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6010 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6011 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6012 SYM_MASK(IntMask, SDmaIntMask_1) |
6013 SYM_MASK(IntMask, ErrIntMask_1) |
6014 SYM_MASK(IntMask, SendDoneIntMask_1));
6203 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6389 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
6390 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
6391 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
6392 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
6542 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6562 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
7115 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7118 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7226 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7275 data &= ~SYM_MASK(IBSerdesCtrl_0, IB_LAT_MODE);
7277 SYM_MASK(IBSerdesCtrl_0, RXLOSEN));
7361 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
7362 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
7363 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
7364 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
7366 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7417 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
7642 SYM_MASK(Control, FreezeMode));
7660 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
7668 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);