Lines Matching refs:cspec
290 if (dd->cspec->cregbase && (dd->flags & QIB_PRESENT))
291 writeq(value, &dd->cspec->cregbase[regno]);
296 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
298 return readq(&dd->cspec->cregbase[regno]);
303 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
305 return readl(&dd->cspec->cregbase[regno]);
903 msg = dd->cspec->sdmamsgbuf;
904 qib_decode_7220_sdma_errs(ppd, errs, msg, sizeof dd->cspec->sdmamsgbuf);
1098 errs &= dd->cspec->errormask;
1099 msg = dd->cspec->emsgbuf;
1103 qib_7220_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1157 qib_decode_7220_err(dd, msg, sizeof dd->cspec->emsgbuf, errs & ~mask);
1279 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1323 hwerrs &= dd->cspec->hwerrmask;
1367 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
1368 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1374 bitsmsg = dd->cspec->bitsmsgbuf;
1380 snprintf(bitsmsg, sizeof dd->cspec->bitsmsgbuf,
1390 snprintf(bitsmsg, sizeof dd->cspec->bitsmsgbuf,
1395 dd->cspec->hwerrmask &= ~(hwerrs & _QIB_PLL_FAIL);
1396 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1404 dd->cspec->hwerrmask &= ~QLOGIC_IB_HWE_SERDESPLLFAILED;
1405 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1451 dd->cspec->hwerrmask = val;
1454 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
1460 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
1475 dd->cspec->errormask |= ERR_MASK(SendPioArmLaunchErr);
1477 dd->cspec->errormask &= ~ERR_MASK(SendPioArmLaunchErr);
1478 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1754 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
1755 extctl = dd->cspec->extctrl & ~(SYM_MASK(EXTCtrl, LEDPriPortGreenOn) |
1769 dd->cspec->extctrl = extctl;
1771 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
1779 if (dd->cspec->irq) {
1780 free_irq(dd->cspec->irq, dd);
1781 dd->cspec->irq = 0;
1796 kfree(dd->cspec->cntrs);
1797 kfree(dd->cspec->portcntrs);
1910 dd->cspec->gpio_mask &= ~gpio_irq;
1911 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2025 if (!dd->cspec->irq)
2029 int ret = request_irq(dd->cspec->irq, qib_7220intr,
2036 "MSI" : "INTx", dd->cspec->irq, ret);
2160 dd->cspec->presets_needed = 1;
2298 dd->cspec->numctxts = nchipctxts;
2327 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2336 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2339 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
2340 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, IBA7220_KRCVEGRCNT);
2489 dd->cspec->presets_needed = 1;
2739 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2808 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3145 dd->cspec->ncntrs = i;
3148 dd->cspec->cntrnamelen = sizeof(cntr7220names) - 1;
3150 dd->cspec->cntrnamelen = 1 + s - cntr7220names;
3151 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
3153 if (!dd->cspec->cntrs)
3158 dd->cspec->nportcntrs = i - 1;
3159 dd->cspec->portcntrnamelen = sizeof(portcntr7220names) - 1;
3160 dd->cspec->portcntrs = kmalloc(dd->cspec->nportcntrs
3162 if (!dd->cspec->portcntrs)
3171 if (!dd->cspec->cntrs) {
3178 ret = dd->cspec->cntrnamelen;
3182 u64 *cntr = dd->cspec->cntrs;
3185 ret = dd->cspec->ncntrs * sizeof(u64);
3193 for (i = 0; i < dd->cspec->ncntrs; i++)
3205 if (!dd->cspec->portcntrs) {
3211 ret = dd->cspec->portcntrnamelen;
3215 u64 *cntr = dd->cspec->portcntrs;
3219 ret = dd->cspec->nportcntrs * sizeof(u64);
3226 for (i = 0; i < dd->cspec->nportcntrs; i++) {
3298 dd->cspec->irq = dd->pcidev->irq;
3343 u32 lbuf = ppd->dd->cspec->lastbuf_for_pio;
3584 if (dd->cspec->autoneg_tries == AUTONEG_TRIES) {
3586 dd->cspec->autoneg_tries = 0;
3661 dd->cspec->autoneg_tries < AUTONEG_TRIES) {
3663 ++dd->cspec->autoneg_tries;
3688 dd->cspec->autoneg_tries = 0;
3774 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
3775 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
3776 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
3777 new_out = (dd->cspec->gpio_out & ~mask) | out;
3779 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
3781 dd->cspec->gpio_out = new_out;
3782 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
3850 * The chip base addresses in cspec and cpspec have to be set
3859 dd->cspec->cregbase = (u64 __iomem *)
3984 dd->cspec = (struct qib_chip_specific *)(cpspec + dd->num_pports);
3987 spin_lock_init(&dd->cspec->sdepb_lock);
3988 spin_lock_init(&dd->cspec->rcvmod_lock);
3989 spin_lock_init(&dd->cspec->gpio_lock);
4125 dd->cspec->sdmabufcnt = dd->piobcnt4k;
4128 dd->cspec->sdmabufcnt = 0;
4132 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
4133 dd->cspec->sdmabufcnt;
4134 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
4135 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
4148 dd->cspec->updthresh_dflt = updthresh;
4149 dd->cspec->updthresh = updthresh;
4177 last = dd->cspec->lastbuf_for_pio;
4273 i = n - dd->cspec->sdmabufcnt;
4383 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
4400 dd->cspec->updthresh != dd->cspec->updthresh_dflt
4404 < dd->cspec->updthresh_dflt)
4409 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
4411 dd->sendctrl |= (dd->cspec->updthresh &
4421 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
4422 dd->cspec->updthresh = (rcd->piocnt /
4425 dd->sendctrl |= (dd->cspec->updthresh &
4595 dd->cspec->irq = pdev->irq;