Lines Matching defs:qib_read_kreg64
357 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
752 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
972 sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror);
973 sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1);
1071 u64 ibcs = qib_read_kreg64(dd, kr_ibcstatus);
1139 extsval = qib_read_kreg64(dd, kr_extstatus);
1165 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
1274 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1275 config1 = qib_read_kreg64(dd, kr_serdes_cfg1);
1291 qib_read_kreg64(dd, kr_scratch);
1311 (void) qib_read_kreg64(dd, kr_scratch);
1323 (void) qib_read_kreg64(dd, kr_scratch);
1325 val = qib_read_kreg64(dd, kr_xgxs_cfg);
1337 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1355 hwstat = qib_read_kreg64(dd, kr_hwerrstatus);
1391 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
1414 val = qib_read_kreg64(dd, kr_serdes_cfg0);
1462 val = qib_read_kreg64(dd, kr_ibcstatus);
1542 estat = qib_read_kreg64(dd, kr_errstatus);
2617 errormask = qib_read_kreg64(dd, kr_errmask);
2623 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2701 prev_val = qib_read_kreg64(dd, kr_xgxs_cfg);
3095 read_val = qib_read_kreg64(dd, kr_extstatus);
3116 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
3121 val = qib_read_kreg64(dd, kr_sendpiosize);
3130 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
3184 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
3355 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3363 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */
3556 if (qib_read_kreg64(dd, kr_hwerrstatus) &