Lines Matching refs:x8
55 #define QIB_7322_Revision_R_ChipRevMajor_LSB 0x8
62 #define QIB_7322_Control_OFFS 0x8
229 #define QIB_7322_IntMask_RcvAvail8IntMask_LSB 0x8
230 #define QIB_7322_IntMask_RcvAvail8IntMask_MSB 0x8
385 #define QIB_7322_IntStatus_RcvAvail8_LSB 0x8
386 #define QIB_7322_IntStatus_RcvAvail8_MSB 0x8
541 #define QIB_7322_IntClear_RcvAvail8IntClear_LSB 0x8
542 #define QIB_7322_IntClear_RcvAvail8IntClear_MSB 0x8
1067 #define QIB_7322_SendBufCnt_Num_SmallBuffers_MSB 0x8
1249 #define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_LSB 0x8
1276 #define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_LSB 0x8
1303 #define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_LSB 0x8
1330 #define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_LSB 0x8
1351 #define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_LSB 0x8
1462 #define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_LSB 0x8
1463 #define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_MSB 0x8
1582 #define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_LSB 0x8
1583 #define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_MSB 0x8
1702 #define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_LSB 0x8
1703 #define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_MSB 0x8
1984 #define QIB_7322_SendCtrl_0_SDmaCleanup_LSB 0x8
1985 #define QIB_7322_SendCtrl_0_SDmaCleanup_MSB 0x8
2218 #define QIB_7322_IBCStatusA_0_LinkSpeedActive_LSB 0x8
2219 #define QIB_7322_IBCStatusA_0_LinkSpeedActive_MSB 0x8
2287 #define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_LSB 0x8
2329 #define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_LSB 0x8
2330 #define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_MSB 0x8
2428 #define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_LSB 0x8
2494 #define QIB_7322_IBSerdesCtrl_0_TXIDLE_LSB 0x8
2495 #define QIB_7322_IBSerdesCtrl_0_TXIDLE_MSB 0x8
2516 #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_MSB 0x8
2557 #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_LSB 0x8
2596 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_LSB 0x8
2635 #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_LSB 0x8
2674 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_LSB 0x8
2713 #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_LSB 0x8
2752 #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_LSB 0x8