Lines Matching defs:rdev_p
71 int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
82 ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup);
114 rdev_p->dev_name);
125 static int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
134 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
137 static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
155 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
158 int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq, int kernel)
163 cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
171 cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev), size,
184 if (rdev_p->t3cdev_p->type != T3A)
188 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
191 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
200 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
203 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
217 qpid = cxio_hal_get_qpid(rdev_p->rscp);
220 for (i = qpid+1; i & rdev_p->qpmask; i++) {
234 static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
249 void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
258 if (!(entry->qpid & rdev_p->qpmask))
259 cxio_hal_put_qpid(rdev_p->rscp, entry->qpid);
265 void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
271 int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
277 wq->qpid = get_qpid(rdev_p, uctx);
285 wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
293 wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
301 wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
303 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
304 (wq->qpid << rdev_p->qpshift);
305 wq->rdev = rdev_p;
312 cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
316 put_qpid(rdev_p, wq->qpid, uctx);
320 int cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
323 err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
325 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
329 cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
333 int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
336 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
341 cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
343 put_qpid(rdev_p, wq->qpid, uctx);
497 static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
508 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
511 static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
524 err = cxio_hal_init_ctrl_cq(rdev_p);
529 rdev_p->ctrl_qp.workq = dma_alloc_coherent(
530 &(rdev_p->rnic_info.pdev->dev),
533 &(rdev_p->ctrl_qp.dma_addr),
535 if (!rdev_p->ctrl_qp.workq) {
540 dma_unmap_addr_set(&rdev_p->ctrl_qp, mapping,
541 rdev_p->ctrl_qp.dma_addr);
542 rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
543 memset(rdev_p->ctrl_qp.workq, 0,
546 mutex_init(&rdev_p->ctrl_qp.lock);
547 init_waitqueue_head(&rdev_p->ctrl_qp.waitq);
550 base_addr = rdev_p->ctrl_qp.dma_addr;
572 (unsigned long long) rdev_p->ctrl_qp.dma_addr,
573 rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
575 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
581 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
583 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
585 * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
586 dma_unmap_addr(&rdev_p->ctrl_qp, mapping));
587 return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
594 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
606 __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
610 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
614 rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
615 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
616 !Q_FULL(rdev_p->ctrl_qp.rptr,
617 rdev_p->ctrl_qp.wptr,
626 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
668 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
672 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
679 Q_GENBIT(rdev_p->ctrl_qp.wptr,
683 ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
685 rdev_p->ctrl_qp.wptr++;
694 static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
705 if (cxio_fatal_error(rdev_p))
712 stag_idx = cxio_hal_get_stag(rdev_p->rscp);
720 mutex_lock(&rdev_p->ctrl_qp.lock);
736 cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3));
744 err = cxio_hal_ctrl_qp_write_mem(rdev_p,
746 (rdev_p->rnic_info.tpt_base >> 5),
751 cxio_hal_put_stag(rdev_p->rscp, stag_idx);
753 wptr = rdev_p->ctrl_qp.wptr;
754 mutex_unlock(&rdev_p->ctrl_qp.lock);
756 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
757 SEQ32_GE(rdev_p->ctrl_qp.rptr,
763 int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
770 __func__, pbl_addr, rdev_p->rnic_info.pbl_base,
773 mutex_lock(&rdev_p->ctrl_qp.lock);
774 err = cxio_hal_ctrl_qp_write_mem(rdev_p, pbl_addr >> 5, pbl_size << 3,
776 wptr = rdev_p->ctrl_qp.wptr;
777 mutex_unlock(&rdev_p->ctrl_qp.lock);
781 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
782 SEQ32_GE(rdev_p->ctrl_qp.rptr,
789 int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
794 return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
798 int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
802 return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
806 int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
809 return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
813 int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
816 return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
820 int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
822 return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
826 int cxio_allocate_stag(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr)
829 return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_NON_SHARED_MR,
833 int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
839 PDBG("%s rdev_p %p\n", __func__, rdev_p);
849 wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
864 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
880 struct cxio_rdev *rdev_p = NULL;
894 rdev_p = (struct cxio_rdev *)t3cdev_p->ulp;
895 if (!rdev_p) {
901 rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
902 wake_up_interruptible(&rdev_p->ctrl_qp.waitq);
907 (*cxio_ev_cb) (rdev_p, skb);
915 int cxio_rdev_open(struct cxio_rdev *rdev_p)
919 if (strlen(rdev_p->dev_name)) {
920 if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) {
923 netdev_p = dev_get_by_name(&init_net, rdev_p->dev_name);
928 } else if (rdev_p->t3cdev_p) {
929 if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) {
932 netdev_p = rdev_p->t3cdev_p->lldev;
933 strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name,
940 list_add_tail(&rdev_p->entry, &rdev_list);
942 PDBG("%s opening rnic dev %s\n", __func__, rdev_p->dev_name);
943 memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
944 if (!rdev_p->t3cdev_p)
945 rdev_p->t3cdev_p = dev2t3cdev(netdev_p);
946 rdev_p->t3cdev_p->ulp = (void *) rdev_p;
948 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_EMBEDDED_INFO,
949 &(rdev_p->fw_info));
952 __func__, rdev_p->t3cdev_p, err);
955 if (G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers) != CXIO_FW_MAJ) {
959 G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers));
964 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS,
965 &(rdev_p->rnic_info));
968 __func__, rdev_p->t3cdev_p, err);
971 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS,
972 &(rdev_p->port_info));
975 __func__, rdev_p->t3cdev_p, err);
983 cxio_init_ucontext(rdev_p, &rdev_p->uctx);
984 rdev_p->qpshift = PAGE_SHIFT -
986 ilog2(rdev_p->rnic_info.udbell_len >>
988 rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
989 rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
992 __func__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base,
993 rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p),
994 rdev_p->rnic_info.pbl_base,
995 rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
996 rdev_p->rnic_info.rqt_top);
999 rdev_p->rnic_info.udbell_len,
1000 rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
1001 rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
1003 err = cxio_hal_init_ctrl_qp(rdev_p);
1009 err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
1017 err = cxio_hal_pblpool_create(rdev_p);
1023 err = cxio_hal_rqtpool_create(rdev_p);
1031 cxio_hal_pblpool_destroy(rdev_p);
1033 cxio_hal_destroy_resource(rdev_p->rscp);
1035 cxio_hal_destroy_ctrl_qp(rdev_p);
1037 rdev_p->t3cdev_p->ulp = NULL;
1038 list_del(&rdev_p->entry);
1042 void cxio_rdev_close(struct cxio_rdev *rdev_p)
1044 if (rdev_p) {
1045 cxio_hal_pblpool_destroy(rdev_p);
1046 cxio_hal_rqtpool_destroy(rdev_p);
1047 list_del(&rdev_p->entry);
1048 cxio_hal_destroy_ctrl_qp(rdev_p);
1049 cxio_hal_destroy_resource(rdev_p->rscp);
1050 rdev_p->t3cdev_p->ulp = NULL;