Lines Matching defs:timings
44 * have the register with the fast PCI bus timings.
66 * Here are the standard PIO mode 0-4 timings for each "format".
67 * Format-0 uses fast data reg timings, with slower command reg timings.
68 * Format-1 uses fast timings for all registers, but won't work with all drives.
77 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
79 //#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
98 * different timings can still be chosen for each drive. We could
129 unsigned int reg, timings;
149 * Note that each DMA mode has several timings associated with it.
154 timings = udma_timing[pci_clock][mode - XFER_UDMA_0];
156 timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];
160 timings |= reg & 0x80000000; /* preserve PIO format bit */
161 pci_write_config_dword(dev, basereg + 4, timings);
163 pci_write_config_dword(dev, basereg + 12, timings);
194 * will have valid default PIO timings set up before we get here.