Lines Matching defs:w83781d_write_value
249 static int w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value);
280 w83781d_write_value(data, W83781D_REG_IN_##REG(nr), data->in_##reg[nr]); \
333 w83781d_write_value(data, W83781D_REG_FAN_MIN(nr),
383 w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
387 w83781d_write_value(data, W83781D_REG_TEMP_##REG(nr), \
500 w83781d_write_value(data, W83781D_REG_BEEP_INTS1,
502 w83781d_write_value(data, W83781D_REG_BEEP_INTS2,
505 w83781d_write_value(data, W83781D_REG_BEEP_INTS3,
549 w83781d_write_value(data, W83781D_REG_BEEP_INTS1, reg);
556 w83781d_write_value(data, W83781D_REG_BEEP_INTS2, reg);
563 w83781d_write_value(data, W83781D_REG_BEEP_INTS3, reg);
647 w83781d_write_value(data, nr==2 ? W83781D_REG_PIN : W83781D_REG_VID_FANDIV, reg);
654 w83781d_write_value(data, W83781D_REG_VBAT, reg);
659 w83781d_write_value(data, W83781D_REG_FAN_MIN(nr), data->fan_min[nr]);
700 w83781d_write_value(data, W83781D_REG_PWM[nr], data->pwm[nr]);
720 w83781d_write_value(data, W83781D_REG_PWMCLK12,
724 w83781d_write_value(data, W83781D_REG_BEEP_CONFIG,
771 w83781d_write_value(data, W83781D_REG_SCFG1,
774 w83781d_write_value(data, W83781D_REG_SCFG2,
780 w83781d_write_value(data, W83781D_REG_SCFG1,
783 w83781d_write_value(data, W83781D_REG_SCFG2,
793 w83781d_write_value(data, W83781D_REG_SCFG1,
841 w83781d_write_value(data, W83781D_REG_I2C_SUBADDR,
1327 w83781d_write_value(data, W83781D_REG_CONFIG, 0x80);
1330 w83781d_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80);
1331 w83781d_write_value(data, W83781D_REG_PWMCLK12, p);
1335 w83781d_write_value(data, W83781D_REG_BEEP_INTS2, 0);
1342 w83781d_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80);
1371 w83781d_write_value(data, W83781D_REG_TEMP2_CONFIG,
1382 w83781d_write_value(data,
1389 w83781d_write_value(data, W83781D_REG_CONFIG,
1686 w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value)
1982 w83781d_write_value(struct w83781d_data *data, u16 reg, u16 value)