Lines Matching defs:bo
41 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
50 struct radeon_bo *bo;
52 bo = container_of(tbo, struct radeon_bo, tbo);
53 mutex_lock(&bo->rdev->gem.mutex);
54 list_del_init(&bo->list);
55 mutex_unlock(&bo->rdev->gem.mutex);
56 radeon_bo_clear_surface_reg(bo);
57 kfree(bo);
60 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
62 if (bo->destroy == &radeon_ttm_bo_destroy)
92 struct radeon_bo *bo;
107 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
108 if (bo == NULL)
110 bo->rdev = rdev;
111 bo->gobj = gobj;
112 bo->surface_reg = -1;
113 INIT_LIST_HEAD(&bo->list);
114 radeon_ttm_placement_from_domain(bo, domain);
117 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
118 &bo->placement, 0, 0, !kernel, NULL, size,
133 *bo_ptr = bo;
135 mutex_lock(&bo->rdev->gem.mutex);
136 list_add_tail(&bo->list, &rdev->gem.objects);
137 mutex_unlock(&bo->rdev->gem.mutex);
142 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
147 if (bo->kptr) {
149 *ptr = bo->kptr;
153 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
157 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
159 *ptr = bo->kptr;
161 radeon_bo_check_tiling(bo, 0, 0);
165 void radeon_bo_kunmap(struct radeon_bo *bo)
167 if (bo->kptr == NULL)
169 bo->kptr = NULL;
170 radeon_bo_check_tiling(bo, 0, 0);
171 ttm_bo_kunmap(&bo->kmap);
174 void radeon_bo_unref(struct radeon_bo **bo)
179 if ((*bo) == NULL)
181 rdev = (*bo)->rdev;
182 tbo = &((*bo)->tbo);
187 *bo = NULL;
190 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
194 if (bo->pin_count) {
195 bo->pin_count++;
197 *gpu_addr = radeon_bo_gpu_offset(bo);
200 radeon_ttm_placement_from_domain(bo, domain);
203 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
205 for (i = 0; i < bo->placement.num_placement; i++)
206 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
207 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
209 bo->pin_count = 1;
211 *gpu_addr = radeon_bo_gpu_offset(bo);
214 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
218 int radeon_bo_unpin(struct radeon_bo *bo)
222 if (!bo->pin_count) {
223 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
226 bo->pin_count--;
227 if (bo->pin_count)
229 for (i = 0; i < bo->placement.num_placement; i++)
230 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
231 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
233 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
250 struct radeon_bo *bo, *n;
257 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
259 gobj = bo->gobj;
261 gobj, bo, (unsigned long)gobj->size,
263 mutex_lock(&bo->rdev->gem.mutex);
264 list_del_init(&bo->list);
265 mutex_unlock(&bo->rdev->gem.mutex);
266 radeon_bo_unref(&bo);
307 r = radeon_bo_reserve(lobj->bo, false);
321 if (lobj->reserved && radeon_bo_is_reserved(lobj->bo))
322 radeon_bo_unreserve(lobj->bo);
329 struct radeon_bo *bo;
341 bo = lobj->bo;
342 if (!bo->pin_count) {
346 radeon_ttm_placement_from_domain(bo, domain);
347 r = ttm_bo_validate(&bo->tbo, &bo->placement,
357 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
358 lobj->tiling_flags = bo->tiling_flags;
366 struct radeon_bo *bo;
370 bo = lobj->bo;
371 spin_lock(&bo->tbo.lock);
372 old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
373 bo->tbo.sync_obj = radeon_fence_ref(fence);
374 bo->tbo.sync_obj_arg = NULL;
375 spin_unlock(&bo->tbo.lock);
382 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
385 return ttm_fbdev_mmap(vma, &bo->tbo);
388 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
390 struct radeon_device *rdev = bo->rdev;
396 BUG_ON(!atomic_read(&bo->tbo.reserved));
398 if (!bo->tiling_flags)
401 if (bo->surface_reg >= 0) {
402 reg = &rdev->surface_regs[bo->surface_reg];
403 i = bo->surface_reg;
411 if (!reg->bo)
414 old_object = reg->bo;
425 old_object = reg->bo;
433 bo->surface_reg = i;
434 reg->bo = bo;
437 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
438 bo->tbo.mem.mm_node->start << PAGE_SHIFT,
439 bo->tbo.num_pages << PAGE_SHIFT);
443 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
445 struct radeon_device *rdev = bo->rdev;
448 if (bo->surface_reg == -1)
451 reg = &rdev->surface_regs[bo->surface_reg];
452 radeon_clear_surface_reg(rdev, bo->surface_reg);
454 reg->bo = NULL;
455 bo->surface_reg = -1;
458 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
463 r = radeon_bo_reserve(bo, false);
466 bo->tiling_flags = tiling_flags;
467 bo->pitch = pitch;
468 radeon_bo_unreserve(bo);
472 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
476 BUG_ON(!atomic_read(&bo->tbo.reserved));
478 *tiling_flags = bo->tiling_flags;
480 *pitch = bo->pitch;
483 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
486 BUG_ON(!atomic_read(&bo->tbo.reserved));
488 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
492 radeon_bo_clear_surface_reg(bo);
496 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
500 if (bo->surface_reg >= 0)
501 radeon_bo_clear_surface_reg(bo);
505 if ((bo->surface_reg >= 0) && !has_moved)
508 return radeon_bo_get_surface_reg(bo);
511 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
515 if (!radeon_ttm_bo_is_radeon_bo(bo))
517 rbo = container_of(bo, struct radeon_bo, tbo);
521 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
528 if (!radeon_ttm_bo_is_radeon_bo(bo))
530 rbo = container_of(bo, struct radeon_bo, tbo);
533 if (bo->mem.mem_type == TTM_PL_VRAM) {
534 size = bo->mem.num_pages << PAGE_SHIFT;
535 offset = bo->mem.mm_node->start << PAGE_SHIFT;
540 r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
543 offset = bo->mem.mm_node->start << PAGE_SHIFT;