Lines Matching refs:pll_ref_div
678 uint32_t pll_ref_div = 0;
737 pll_ref_div = lvds->panel_ref_divider;
771 pll_ref_div = reference_div;
779 pll_ref_div & 0x3ff,
789 &pll_ref_div, &pll_fb_post_div,
806 pll_ref_div,
829 (unsigned)pll_ref_div,
834 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
852 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
857 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
890 if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
895 pll_ref_div,
900 (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
905 pll_ref_div,
929 pll_ref_div,
934 pll_ref_div & RADEON_PPLL_REF_DIV_MASK,