Lines Matching refs:dev_priv
40 drm_radeon_private_t *dev_priv = dev->dev_private;
43 dev_priv->irq_enable_reg |= mask;
45 dev_priv->irq_enable_reg &= ~mask;
48 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
53 drm_radeon_private_t *dev_priv = dev->dev_private;
56 dev_priv->r500_disp_irq_reg |= mask;
58 dev_priv->r500_disp_irq_reg &= ~mask;
61 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
66 drm_radeon_private_t *dev_priv = dev->dev_private;
68 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
101 drm_radeon_private_t *dev_priv = dev->dev_private;
103 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
132 static inline u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 *r500_disp_int)
138 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
186 drm_radeon_private_t *dev_priv =
191 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
197 stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
201 stat &= dev_priv->irq_enable_reg;
205 DRM_WAKEUP(&dev_priv->swi_queue);
208 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
224 drm_radeon_private_t *dev_priv = dev->dev_private;
228 atomic_inc(&dev_priv->swi_emitted);
229 ret = atomic_read(&dev_priv->swi_emitted);
242 drm_radeon_private_t *dev_priv =
249 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
251 DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
259 drm_radeon_private_t *dev_priv = dev->dev_private;
261 if (!dev_priv) {
271 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
288 drm_radeon_private_t *dev_priv = dev->dev_private;
292 if (!dev_priv) {
297 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
316 drm_radeon_private_t *dev_priv = dev->dev_private;
319 if (!dev_priv) {
324 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
334 drm_radeon_private_t *dev_priv =
338 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
342 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
347 radeon_acknowledge_irqs(dev_priv, &dummy);
352 drm_radeon_private_t *dev_priv =
355 atomic_set(&dev_priv->swi_emitted, 0);
356 DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
360 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
370 drm_radeon_private_t *dev_priv =
372 if (!dev_priv)
375 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
378 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
387 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
389 return dev_priv->vblank_crtc;
394 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
399 dev_priv->vblank_crtc = (unsigned int)value;