Lines Matching refs:dev_priv
332 extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
333 extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
335 #define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv)
336 #define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)
341 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
344 u32 fb_start = dev_priv->fb_location;
345 u32 fb_end = fb_start + dev_priv->fb_size - 1;
346 u32 gart_start = dev_priv->gart_vm_start;
347 u32 gart_end = gart_start + dev_priv->gart_size - 1;
366 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
367 extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
368 extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
369 extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr);
374 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
376 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
389 extern void radeon_enable_bm(struct drm_radeon_private *dev_priv);
390 extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off);
391 extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val);
441 extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv);
442 extern void r600_do_cp_start(drm_radeon_private_t *dev_priv);
443 extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv);
444 extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv);
743 extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
745 #define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
1850 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1854 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1856 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1857 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1860 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1861 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1907 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1908 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
1910 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \
1956 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1966 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1976 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1986 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
2001 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
2003 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
2004 u32 head = GET_RING_HEAD( dev_priv ); \
2005 if (head == dev_priv->ring.tail) \
2006 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
2010 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
2016 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
2017 __ret = r600_do_cp_idle(dev_priv); \
2019 __ret = radeon_do_cp_idle(dev_priv); \
2073 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN-1)); \
2075 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \
2077 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \
2079 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
2080 ring = dev_priv->ring.start; \
2081 write = dev_priv->ring.tail; \
2082 mask = dev_priv->ring.tail_mask; \
2088 write, dev_priv->ring.tail ); \
2090 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
2093 ((dev_priv->ring.tail + _nr) & mask), \
2096 dev_priv->ring.tail = write; \
2099 extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
2102 radeon_commit_ring(dev_priv); \