Lines Matching refs:radeon_crtc
36 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
40 cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
45 WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
47 cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
52 WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
54 cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
59 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
65 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
69 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
72 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
75 switch (radeon_crtc->crtc_id) {
91 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
95 WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
99 WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
103 switch (radeon_crtc->crtc_id) {
123 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
127 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 0);
128 WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
131 if (radeon_crtc->crtc_id)
136 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
138 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
140 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
150 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
167 radeon_crtc->cursor_width = width;
168 radeon_crtc->cursor_height = height;
172 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
186 if (radeon_crtc->cursor_bo) {
187 radeon_gem_object_unpin(radeon_crtc->cursor_bo);
188 drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
191 radeon_crtc->cursor_bo = obj;
202 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 int w = radeon_crtc->cursor_width;
252 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset,
255 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
256 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
257 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
259 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
262 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
263 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
264 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
269 WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
273 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
278 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +