Lines Matching refs:dev_priv
45 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr)
60 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) &&
61 ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) {
103 cp_set_surface_sync(drm_radeon_private_t *dev_priv,
127 drm_radeon_private_t *dev_priv = dev->dev_private;
136 vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset);
137 ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256);
144 dev_priv->blit_vb->used = 512;
146 gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset;
183 cp_set_surface_sync(dev_priv,
188 set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr)
208 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
209 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
210 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
211 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
212 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
213 cp_set_surface_sync(dev_priv,
216 cp_set_surface_sync(dev_priv,
221 set_tex_resource(drm_radeon_private_t *dev_priv,
259 set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2)
283 draw_auto(drm_radeon_private_t *dev_priv)
308 set_default_state(drm_radeon_private_t *dev_priv)
318 switch ((dev_priv->flags & RADEON_FAMILY_MASK)) {
432 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
433 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
434 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
435 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
436 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
462 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
513 drm_radeon_private_t *dev_priv = dev->dev_private;
514 dev_priv->blit_vb = radeon_freelist_get(dev);
515 if (!dev_priv->blit_vb) {
524 drm_radeon_private_t *dev_priv = dev->dev_private;
526 dev_priv->blit_vb->used = 0;
527 radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->master, dev_priv->blit_vb);
532 drm_radeon_private_t *dev_priv = dev->dev_private;
534 dev_priv->blit_vb->offset + dev_priv->blit_vb->used));
540 drm_radeon_private_t *dev_priv = dev->dev_private;
548 dev_priv->blit_vb->file_priv = file_priv;
550 set_default_state(dev_priv);
560 drm_radeon_private_t *dev_priv = dev->dev_private;
583 drm_radeon_private_t *dev_priv = dev->dev_private;
618 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
622 if (!dev_priv->blit_vb)
644 set_tex_resource(dev_priv, FMT_8,
648 cp_set_surface_sync(dev_priv,
652 set_render_target(dev_priv, COLOR_8,
657 set_scissors(dev_priv, dst_x, 0, dst_x + cur_size, h);
660 vb_addr = dev_priv->gart_buffers_offset +
661 dev_priv->blit_vb->offset +
662 dev_priv->blit_vb->used;
663 set_vtx_resource(dev_priv, vb_addr);
666 draw_auto(dev_priv);
668 cp_set_surface_sync(dev_priv,
673 dev_priv->blit_vb->used += 12 * 4;
707 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
710 if (!dev_priv->blit_vb)
733 set_tex_resource(dev_priv, FMT_8_8_8_8,
738 cp_set_surface_sync(dev_priv,
742 set_render_target(dev_priv, COLOR_8_8_8_8,
747 set_scissors(dev_priv, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
750 vb_addr = dev_priv->gart_buffers_offset +
751 dev_priv->blit_vb->offset +
752 dev_priv->blit_vb->used;
753 set_vtx_resource(dev_priv, vb_addr);
756 draw_auto(dev_priv);
758 cp_set_surface_sync(dev_priv,
763 dev_priv->blit_vb->used += 12 * 4;
778 drm_radeon_private_t *dev_priv = dev->dev_private;
784 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
788 if (!dev_priv->blit_vb)
831 set_tex_resource(dev_priv, tex_format,
836 cp_set_surface_sync(dev_priv,
840 set_render_target(dev_priv, cb_format,
845 set_scissors(dev_priv, dx, dy, dx2, dy2);
848 vb_addr = dev_priv->gart_buffers_offset +
849 dev_priv->blit_vb->offset +
850 dev_priv->blit_vb->used;
851 set_vtx_resource(dev_priv, vb_addr);
854 draw_auto(dev_priv);
856 cp_set_surface_sync(dev_priv,
860 dev_priv->blit_vb->used += 12 * 4;