Lines Matching defs:rdev
36 static int r520_mc_wait_for_idle(struct radeon_device *rdev)
41 for (i = 0; i < rdev->usec_timeout; i++) {
52 static void r520_gpu_init(struct radeon_device *rdev)
56 rv515_vga_render_disable(rdev);
77 if (rdev->family == CHIP_RV530) {
80 r420_pipes_init(rdev);
87 if (r520_mc_wait_for_idle(rdev)) {
93 static void r520_vram_get_type(struct radeon_device *rdev)
97 rdev->mc.vram_width = 128;
98 rdev->mc.vram_is_ddr = true;
102 rdev->mc.vram_width = 32;
105 rdev->mc.vram_width = 64;
108 rdev->mc.vram_width = 128;
111 rdev->mc.vram_width = 256;
114 rdev->mc.vram_width = 128;
118 rdev->mc.vram_width *= 2;
121 void r520_mc_init(struct radeon_device *rdev)
124 r520_vram_get_type(rdev);
125 r100_vram_init_sizes(rdev);
126 radeon_vram_location(rdev, &rdev->mc, 0);
127 rdev->mc.gtt_base_align = 0;
128 if (!(rdev->flags & RADEON_IS_AGP))
129 radeon_gtt_location(rdev, &rdev->mc);
130 radeon_update_bandwidth_info(rdev);
133 void r520_mc_program(struct radeon_device *rdev)
138 rv515_mc_stop(rdev, &save);
141 if (r520_mc_wait_for_idle(rdev))
142 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
144 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
147 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
148 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
150 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
151 if (rdev->flags & RADEON_IS_AGP) {
153 S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) |
154 S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
155 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
157 S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
164 rv515_mc_resume(rdev, &save);
167 static int r520_startup(struct radeon_device *rdev)
171 r520_mc_program(rdev);
173 rv515_clock_startup(rdev);
175 r520_gpu_init(rdev);
178 if (rdev->flags & RADEON_IS_PCIE) {
179 r = rv370_pcie_gart_enable(rdev);
184 rs600_irq_set(rdev);
185 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
187 r = r100_cp_init(rdev, 1024 * 1024);
189 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
192 r = r100_wb_init(rdev);
194 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
195 r = r100_ib_init(rdev);
197 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
203 int r520_resume(struct radeon_device *rdev)
206 if (rdev->flags & RADEON_IS_PCIE)
207 rv370_pcie_gart_disable(rdev);
209 rv515_clock_startup(rdev);
211 if (radeon_asic_reset(rdev)) {
212 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
217 atom_asic_init(rdev->mode_info.atom_context);
219 rv515_clock_startup(rdev);
221 radeon_surface_init(rdev);
222 return r520_startup(rdev);
225 int r520_init(struct radeon_device *rdev)
230 radeon_scratch_init(rdev);
232 radeon_surface_init(rdev);
234 r100_restore_sanity(rdev);
237 if (!radeon_get_bios(rdev)) {
238 if (ASIC_IS_AVIVO(rdev))
241 if (rdev->is_atom_bios) {
242 r = radeon_atombios_init(rdev);
246 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
250 if (radeon_asic_reset(rdev)) {
251 dev_warn(rdev->dev,
257 if (radeon_boot_test_post_card(rdev) == false)
260 if (!radeon_card_posted(rdev) && rdev->bios) {
262 atom_asic_init(rdev->mode_info.atom_context);
265 radeon_get_clock_info(rdev->ddev);
267 if (rdev->flags & RADEON_IS_AGP) {
268 r = radeon_agp_init(rdev);
270 radeon_agp_disable(rdev);
274 r520_mc_init(rdev);
275 rv515_debugfs(rdev);
277 r = radeon_fence_driver_init(rdev);
280 r = radeon_irq_kms_init(rdev);
284 r = radeon_bo_init(rdev);
287 r = rv370_pcie_gart_init(rdev);
290 rv515_set_safe_registers(rdev);
291 rdev->accel_working = true;
292 r = r520_startup(rdev);
295 dev_err(rdev->dev, "Disabling GPU acceleration\n");
296 r100_cp_fini(rdev);
297 r100_wb_fini(rdev);
298 r100_ib_fini(rdev);
299 radeon_irq_kms_fini(rdev);
300 rv370_pcie_gart_fini(rdev);
301 radeon_agp_fini(rdev);
302 rdev->accel_working = false;