Lines Matching defs:rdev
39 void r420_pm_init_profile(struct radeon_device *rdev)
42 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
43 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
44 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
45 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
49 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
50 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
52 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
53 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
54 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
55 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
57 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
58 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
59 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
60 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
62 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
63 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
64 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
65 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
67 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
68 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
69 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
70 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
72 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
73 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
74 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
75 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
78 static void r420_set_reg_safe(struct radeon_device *rdev)
80 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
81 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
84 void r420_pipes_init(struct radeon_device *rdev)
93 if (r100_gui_wait_for_idle(rdev)) {
102 if ((rdev->pdev->device == 0x5e4c) ||
103 (rdev->pdev->device == 0x5e4f))
106 rdev->num_gb_pipes = num_pipes;
129 if (r100_gui_wait_for_idle(rdev)) {
142 if (r100_gui_wait_for_idle(rdev)) {
147 if (rdev->family == CHIP_RV530) {
150 rdev->num_z_pipes = 2;
152 rdev->num_z_pipes = 1;
154 rdev->num_z_pipes = 1;
157 rdev->num_gb_pipes, rdev->num_z_pipes);
160 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg)
169 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
176 static void r420_debugfs(struct radeon_device *rdev)
178 if (r100_debugfs_rbbm_init(rdev)) {
181 if (r420_debugfs_pipes_info_init(rdev)) {
186 static void r420_clock_resume(struct radeon_device *rdev)
191 radeon_atom_set_clock_gating(rdev, 1);
194 if (rdev->family == CHIP_R420)
199 static void r420_cp_errata_init(struct radeon_device *rdev)
201 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
202 radeon_ring_lock(rdev, 8);
203 radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
204 radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
205 radeon_ring_write(rdev, 0xDEADBEEF);
206 radeon_ring_unlock_commit(rdev);
209 static void r420_cp_errata_fini(struct radeon_device *rdev)
214 radeon_ring_lock(rdev, 8);
215 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
216 radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
217 radeon_ring_unlock_commit(rdev);
218 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
221 static int r420_startup(struct radeon_device *rdev)
226 r100_set_common_regs(rdev);
228 r300_mc_program(rdev);
230 r420_clock_resume(rdev);
233 if (rdev->flags & RADEON_IS_PCIE) {
234 r = rv370_pcie_gart_enable(rdev);
238 if (rdev->flags & RADEON_IS_PCI) {
239 r = r100_pci_gart_enable(rdev);
243 r420_pipes_init(rdev);
245 r100_irq_set(rdev);
246 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
248 r = r100_cp_init(rdev, 1024 * 1024);
250 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
253 r420_cp_errata_init(rdev);
254 r = r100_wb_init(rdev);
256 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
258 r = r100_ib_init(rdev);
260 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
266 int r420_resume(struct radeon_device *rdev)
269 if (rdev->flags & RADEON_IS_PCIE)
270 rv370_pcie_gart_disable(rdev);
271 if (rdev->flags & RADEON_IS_PCI)
272 r100_pci_gart_disable(rdev);
274 r420_clock_resume(rdev);
276 if (radeon_asic_reset(rdev)) {
277 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
282 if (rdev->is_atom_bios) {
283 atom_asic_init(rdev->mode_info.atom_context);
285 radeon_combios_asic_init(rdev->ddev);
288 r420_clock_resume(rdev);
290 radeon_surface_init(rdev);
291 return r420_startup(rdev);
294 int r420_suspend(struct radeon_device *rdev)
296 r420_cp_errata_fini(rdev);
297 r100_cp_disable(rdev);
298 r100_wb_disable(rdev);
299 r100_irq_disable(rdev);
300 if (rdev->flags & RADEON_IS_PCIE)
301 rv370_pcie_gart_disable(rdev);
302 if (rdev->flags & RADEON_IS_PCI)
303 r100_pci_gart_disable(rdev);
307 void r420_fini(struct radeon_device *rdev)
309 r100_cp_fini(rdev);
310 r100_wb_fini(rdev);
311 r100_ib_fini(rdev);
312 radeon_gem_fini(rdev);
313 if (rdev->flags & RADEON_IS_PCIE)
314 rv370_pcie_gart_fini(rdev);
315 if (rdev->flags & RADEON_IS_PCI)
316 r100_pci_gart_fini(rdev);
317 radeon_agp_fini(rdev);
318 radeon_irq_kms_fini(rdev);
319 radeon_fence_driver_fini(rdev);
320 radeon_bo_fini(rdev);
321 if (rdev->is_atom_bios) {
322 radeon_atombios_fini(rdev);
324 radeon_combios_fini(rdev);
326 kfree(rdev->bios);
327 rdev->bios = NULL;
330 int r420_init(struct radeon_device *rdev)
335 radeon_scratch_init(rdev);
337 radeon_surface_init(rdev);
340 r100_restore_sanity(rdev);
342 if (!radeon_get_bios(rdev)) {
343 if (ASIC_IS_AVIVO(rdev))
346 if (rdev->is_atom_bios) {
347 r = radeon_atombios_init(rdev);
352 r = radeon_combios_init(rdev);
358 if (radeon_asic_reset(rdev)) {
359 dev_warn(rdev->dev,
365 if (radeon_boot_test_post_card(rdev) == false)
369 radeon_get_clock_info(rdev->ddev);
371 if (rdev->flags & RADEON_IS_AGP) {
372 r = radeon_agp_init(rdev);
374 radeon_agp_disable(rdev);
378 r300_mc_init(rdev);
379 r420_debugfs(rdev);
381 r = radeon_fence_driver_init(rdev);
385 r = radeon_irq_kms_init(rdev);
390 r = radeon_bo_init(rdev);
394 if (rdev->family == CHIP_R420)
395 r100_enable_bm(rdev);
397 if (rdev->flags & RADEON_IS_PCIE) {
398 r = rv370_pcie_gart_init(rdev);
402 if (rdev->flags & RADEON_IS_PCI) {
403 r = r100_pci_gart_init(rdev);
407 r420_set_reg_safe(rdev);
408 rdev->accel_working = true;
409 r = r420_startup(rdev);
412 dev_err(rdev->dev, "Disabling GPU acceleration\n");
413 r100_cp_fini(rdev);
414 r100_wb_fini(rdev);
415 r100_ib_fini(rdev);
416 radeon_irq_kms_fini(rdev);
417 if (rdev->flags & RADEON_IS_PCIE)
418 rv370_pcie_gart_fini(rdev);
419 if (rdev->flags & RADEON_IS_PCI)
420 r100_pci_gart_fini(rdev);
421 radeon_agp_fini(rdev);
422 rdev->accel_working = false;
435 struct radeon_device *rdev = dev->dev_private;
452 int r420_debugfs_pipes_info_init(struct radeon_device *rdev)
455 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1);